**From:** Jeff Cain (*jcain@cisco.com*)

**Date:** Thu Oct 21 1999 - 17:24:30 PDT

**Next message:**Vinu Arumugham: "Re: [SI-LIST] : Effect of low Zo for unterminated lines"**Previous message:**D. C. Sessions: "Re: [SI-LIST] : Effect of low Zo for unterminated lines"**In reply to:**Larry Smith: "RE: [SI-LIST] : Thin Power Plane Dielectrics"

At one time I actually showed this using an FDTD scheme. The actual "effective" dielectric constant

approaches an asymptote as you add more and more vias. Using the same dielectric constants, 4 and 16,

the "effective" dieletric constant approaches 7.2. So doing the square root stuff leads to an increase of

the velocity by a factor of 0.34, which is indeed very close to Larry's solution.

Not only did the above result come as a pleasant surprise, when we added striplines the propogation

delay did not change. That is to say whether we via-ed the two planes together or not, didn't change the

velocity of the waves on that line.

Larry Smith wrote:

*> > From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
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*> >
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*> > An interesting question is what happens if you have a power/ground sandwich
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*> > around a high-Er material and another around a low-Er material, with the two
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*> > sets of planes stitched together regularly, which is what I think Tom
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*> > Woodward was asking. Can that let your noise source get access to more
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*> > "points" on the high-Er sandwich?
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*> >
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*> > Andy
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*>
*

*> Andy - You bring up an interesting question that I considered some time
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*> ago. Suppose we have the stackup below with two parallel power planes
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*> referenced to a center ground plane. The relative permitivity of one
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*> dielectric is 4 and the other is 16:
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*>
*

*> ======================== Vdd plane ======================
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*>
*

*> eR=4 Vel = 0.5 * light
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*>
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*> ======================== Gnd plane ======================
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*>
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*> eR=16 Vel = 0.25 * light
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*>
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*> ======================== Vdd plane ======================
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*>
*

*> If we started a plane wave on the edge of the PCB by stimulating each
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*> Vdd plane wrt the Gnd plane, a disturbance would propagate on the top
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*> layer wrt Gnd at half the speed of light (velocity is proportional to
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*> 1/sqrt(eR) ) and at 1/4 the speed of light on the bottom plane. At the
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*> frequencies that we are concerned about in signal integrity, skin
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*> effect will keep the current on the top surface of the ground plane
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*> away from the bottom surface of the ground plane, and the top and
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*> bottom disturbances just move down the PCB without interfering with
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*> each other, one twice as fast as the other. The velocity is 1/sqrt(LC)
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*> where L is the inductance per inch and C is the capacitance per inch
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*> (easily calculated). If the dielectric thicknesses are the same, the
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*> capacitance of the bottom plane is 4x the capacitance of the top
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*> plane.
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*>
*

*> Now suppose we stitch vias from the top Vdd plane to the bottom Vdd
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*> plane at regular intervals along the way. Neglecting the inductance of
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*> the vias, the top and bottom plane must be at the same potential wrt
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*> the Gnd plane. The wavefront on the top and bottom plane must now move
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*> at the same velocity, or at least re-adjust themselves at every via
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*> along the way.
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*>
*

*> A good way to look at the stitched-together power planes is capacitors
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*> in parallel and inductors in parallel. It turns out that the
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*> inductance per inch of the connected power planes is half of the two
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*> independent power planes. The capacitance per inch is C + 4C = 5C,
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*> where C is the capacitance per inch of the top power plane and L is the
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*> inductance per inch of either power plane. So the velocity of the
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*> combined planes is 1/sqrt(0.5L*5C) = 1/sqrt(LC) * 1/sqrt(2.5). It ends
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*> up being 0.316 times the speed of light, which is somewhere between the
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*> velocity of each individual dielectric.
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*>
*

*> In a real PCB, an ASIC or uP that draws power from the power plane is
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*> likely to located in the center of the board. In this case, a radial
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*> disturbance will emanate out from the noise source at a velocity that
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*> is consistent with the combined dielectrics.
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*>
*

*> Hans Mellberg brought up the possibility of these same power planes
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*> providing return current for signal traces. This is certainly possible
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*> and commonly done. If there are signal traces adjacent to the Vdd
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*> planes (top and bottom in the above stackup), signals on those traces
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*> propagate at the velocity of light reduced by 1/sqrt(eR) where eR is
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*> the relative permitivity of whatever dielectric is between the trace
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*> and the Vdd plane. Once again, with copper power planes of normal
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*> thickness (1 or 1/2 oz copper), skin effect prevents any coupling
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*> between power plane currents and signal return currents at the
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*> frequencies that we are concerned about in signal integrity (greater
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*> than 10 MHz).
*

*>
*

*> regards,
*

*> Larry Smith
*

*> Sun Microsystems
*

*>
*

*> **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
*

-- Jeff Cain Technical Leader Cisco Systems 170 W Tasman SJ-G1 Santa Clara, CA 95134 408-527-7754 408-526-6899**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

**Next message:**Vinu Arumugham: "Re: [SI-LIST] : Effect of low Zo for unterminated lines"**Previous message:**D. C. Sessions: "Re: [SI-LIST] : Effect of low Zo for unterminated lines"**In reply to:**Larry Smith: "RE: [SI-LIST] : Thin Power Plane Dielectrics"

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