**From:** Tom Woodward (*[email protected]*)

**Date:** Thu Oct 21 1999 - 12:33:17 PDT

**Next message:**[email protected]: "Re: AW: [SI-LIST] : Effect of low Zo for unterminated lines"**Previous message:**Larry Smith: "RE: [SI-LIST] : Thin Power Plane Dielectrics"

*>> From: "Ingraham, Andrew" <[email protected]>
*

*>>
*

*>> An interesting question is what happens if you have a power/ground sandwich
*

*>> around a high-Er material and another around a low-Er material, with the two
*

*>> sets of planes stitched together regularly, which is what I think Tom
*

*>> Woodward was asking. Can that let your noise source get access to more
*

*>> "points" on the high-Er sandwich?
*

*>>
*

*>> Andy
*

This is indeed the question I was asking about. I've got a related question ---

see below.

*>
*

*>Andy - You bring up an interesting question that I considered some time
*

*>ago. Suppose we have the stackup below with two parallel power planes
*

*>referenced to a center ground plane. The relative permitivity of one
*

*>dielectric is 4 and the other is 16:
*

*>
*

*>
*

*> ======================== Vdd plane ======================
*

*>
*

*> eR=4 Vel = 0.5 * light
*

*>
*

*> ======================== Gnd plane ======================
*

*>
*

*> eR=16 Vel = 0.25 * light
*

*>
*

*> ======================== Vdd plane ======================
*

*>
*

*>If we started a plane wave on the edge of the PCB by stimulating each
*

*>Vdd plane wrt the Gnd plane, a disturbance would propagate on the top
*

*>layer wrt Gnd at half the speed of light (velocity is proportional to
*

*>1/sqrt(eR) ) and at 1/4 the speed of light on the bottom plane. At the
*

*>frequencies that we are concerned about in signal integrity, skin
*

*>effect will keep the current on the top surface of the ground plane
*

*>away from the bottom surface of the ground plane, and the top and
*

*>bottom disturbances just move down the PCB without interfering with
*

*>each other, one twice as fast as the other. The velocity is 1/sqrt(LC)
*

*>where L is the inductance per inch and C is the capacitance per inch
*

*>(easily calculated). If the dielectric thicknesses are the same, the
*

*>capacitance of the bottom plane is 4x the capacitance of the top
*

*>plane.
*

*>
*

*>Now suppose we stitch vias from the top Vdd plane to the bottom Vdd
*

*>plane at regular intervals along the way. Neglecting the inductance of
*

*>the vias, the top and bottom plane must be at the same potential wrt
*

*>the Gnd plane. The wavefront on the top and bottom plane must now move
*

*>at the same velocity, or at least re-adjust themselves at every via
*

*>along the way.
*

*>
*

*>A good way to look at the stitched-together power planes is capacitors
*

*>in parallel and inductors in parallel. It turns out that the
*

*>inductance per inch of the connected power planes is half of the two
*

*>independent power planes. The capacitance per inch is C + 4C = 5C,
*

*>where C is the capacitance per inch of the top power plane and L is the
*

*>inductance per inch of either power plane. So the velocity of the
*

*>combined planes is 1/sqrt(0.5L*5C) = 1/sqrt(LC) * 1/sqrt(2.5). It ends
*

*>up being 0.316 times the speed of light, which is somewhere between the
*

*>velocity of each individual dielectric.
*

*>
*

*>In a real PCB, an ASIC or uP that draws power from the power plane is
*

*>likely to located in the center of the board. In this case, a radial
*

*>disturbance will emanate out from the noise source at a velocity that
*

*>is consistent with the combined dielectrics.
*

*>
*

*>Hans Mellberg brought up the possibility of these same power planes
*

*>providing return current for signal traces. This is certainly possible
*

*>and commonly done. If there are signal traces adjacent to the Vdd
*

*>planes (top and bottom in the above stackup), signals on those traces
*

*>propagate at the velocity of light reduced by 1/sqrt(eR) where eR is
*

*>the relative permitivity of whatever dielectric is between the trace
*

*>and the Vdd plane. Once again, with copper power planes of normal
*

*>thickness (1 or 1/2 oz copper), skin effect prevents any coupling
*

*>between power plane currents and signal return currents at the
*

*>frequencies that we are concerned about in signal integrity (greater
*

*>than 10 MHz).
*

*>
*

*>regards,
*

*>Larry Smith
*

*>Sun Microsystems
*

Now suppose that the ground and power planes are perforated by

the anti-pads of many vias. Each anti-pad in a plane provides a skin

connection between the top and bottom surfaces of that plane. How

would the disturbances propagating on the top and bottom surfaces

interact with each other at these connection points?

**** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

**Next message:**[email protected]: "Re: AW: [SI-LIST] : Effect of low Zo for unterminated lines"**Previous message:**Larry Smith: "RE: [SI-LIST] : Thin Power Plane Dielectrics"

*
This archive was generated by hypermail 2b29
: Tue Feb 29 2000 - 11:39:17 PST
*