RE: [SI-LIST] : Thin Power Plane Dielectrics

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From: Ingraham, Andrew ([email protected])
Date: Thu Oct 21 1999 - 08:03:01 PDT

>The intent of the burried capacitance layer is to
>provide close proximity decoupling for the higher
>frequencies. It is not usually intended to be the
>image plane of signals as the burried capacitance is
>between gnd and V.

That is correct; however, the power/ground transients also "propagate"
through power/ground planes.

Consider a high Er layer surrounded by a ground plane and a power plane,
with a noisy IC placed in the middle of the board with connections from its
ground and power pins through vias to the appropriate layers. The IC
introduces a transient into the power/ground system at its point of contact.
This transient moves out along (or between) the power and ground layers,
moving outwards in a circular fashion from the IC to the rest of the board.
This propagation velocity is slower because of the high Er material. The
result is that it takes longer for the transient to encompass the same board
area, as a board with a normal Er.

True, it doesn't directly affect any signals (except maybe briefly for those
passing through vias). But it does affect how quickly transients in the
power net can be dissipated.

An interesting question is what happens if you have a power/ground sandwich
around a high-Er material and another around a low-Er material, with the two
sets of planes stitched together regularly, which is what I think Tom
Woodward was asking. Can that let your noise source get access to more
"points" on the high-Er sandwich?


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