**From:** Vinu Arumugham (*vinu@cisco.com*)

**Date:** Tue Oct 19 1999 - 12:07:37 PDT

**Next message:**Dan Bostan: "Re: [SI-LIST] : Effect of low Zo for unterminated lines"**Previous message:**Raymond.Leung@qsa.idt.com: "Re: [SI-LIST] : Effect of low Zo for unterminated lines"**Next in thread:**Craig Twardy: "Re: [SI-LIST] : Thin Power Plane Dielectrics"

One advantage may be that since a smaller area of the plane is depleted, the same area can supply say two chips instead of one if a higher Er material is used.

Vinu

Ray Anderson wrote:

*> Andrew.Ingraham@compaq.com wrote:
*

*>
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*> > I have seen warnings about "buried capacitance" layers that use high-Er
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*> > materials. While this is OK at lower frequencies, the advantage falls apart
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*> > at higher frequencies because the propagation delay through the buried
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*> > capacitance layer is more. Even though the capacitance per unit area is
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*> > large, the capacitance per nanosecond (risetime) may not be.
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*> >
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*> > Andy
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*>
*

*> A good point! The main argument usually made regarding the use of of
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*> high Er dielectric materials is that they enable the inclusion of very
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*> high amounts of capacitance/area in a PCB. While this is true, there
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*> is more to be considered.
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*>
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*> While a high Er constant enables a higher capacitance, it also has another
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*> effect: that of slowing down the time of flight of signal associated with
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*> the high Er dielectric layer.
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*>
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*> Consider the scenario where a planar stackup is modified only by
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*> changing the Er of the substrate material from say 4.0 to 40 .
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*> Let's analyze what happens:
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*>
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*> First the capacitance per unit area within the layer increases by the
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*> ratio of the dielectric constants since:
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*>
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*> Eo*Er*A
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*> C = -------
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*> D
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*>
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*> (changing Er from 4 to 40 causes capacitance/unit area to increase 10X)
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*>
*

*>
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*> Second, the time of flight increases by the square root of the ratio of
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*> the dielectric constants since:
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*>
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*> Dist
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*> Tf = ---------
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*> C/sqrt(Er)
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*>
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*> (changing Er from 4 to 40 causes Tof to increase 3.16 times)
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*>
*

*>
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*> Since the time of flight has increased, it takes longer for charge stored in
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*> the dielectric to reach a "point of consumption" or sink point on the plane.
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*> So if a circuit needs current in say 1ns and charge is traveling 1/3.16
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*> slower then the radius of the "effective capacitance" is 1/3.16 the size
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*> of the original radius.
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*>
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*> We know that the area of a circle is: A= (pi * r^2) . So if the radius
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*> is 1/3.16 the original then the area is 1/10 the original area.
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*>
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*> Since the capacitance / unit area increased 10 X then the
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*> "available capacitance" is 1/10 * 10 = 1 X the original !
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*>
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*> Therefore even though the capacitance per unit area has increased
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*> 10X, the available capacitance to supply current within a specified
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*> time hasn't increased a bit. At lower frequencies the slowing of the
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*> time of flight isn't an issue, but then again we usually aren't depending
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*> on the charge storage capailities of the planes at those frequencies anyway.
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*>
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*> Decreasing the separation between the planes WILL improve matters. Making
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*> the interplanar spacing 1/10 of the original spacing increases the
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*> capacitance by a factor of 10 and doesn't affect the speed of propagation.
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*> In addition, the close plane spacing reduces the planar spreading inductance
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*> giving you a big gain there too.
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*>
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*>
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*> Ray Anderson
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*> Sun Microsystems Inc.
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*>
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*>
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*>
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*

**Next message:**Dan Bostan: "Re: [SI-LIST] : Effect of low Zo for unterminated lines"**Previous message:**Raymond.Leung@qsa.idt.com: "Re: [SI-LIST] : Effect of low Zo for unterminated lines"**Next in thread:**Craig Twardy: "Re: [SI-LIST] : Thin Power Plane Dielectrics"

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