From: sweir ([email protected])
Date: Wed Oct 20 1999 - 10:03:32 PDT
If I understand your comment, I don't believe that idea works. Er is an
expression of what we observe, which is the reduction in propagation
velocity. Any additional parallel planes would constitute new capacitors
in parallel, but the available capacitance / time will still be that of a
the additional parallel plates in a vacuum.
At 09:28 AM 10/20/99 -0400, you wrote:
>Is there another high frequency current path that could mitigate the
>effects of the slow propagation across the high-Er material?
>Due to skin effect, the high frequency current should flow predominately
>in the surface of the power/ground planes adjacent to the high-Er
>dielectric. If the opposite sides of the planes, however, are adjacent
>to normal FR-4, then a higher speed propagation path should
>be available on those surfaces. Nearby power/gnd vias should
>provide a wrap-around path for these currents to reach the surfaces
>adjacent to the high-Er material, thereby allowing earlier access
>to "patches" of higher capacitance. Is this realistic?
>Tom Woodward ([email protected])
>Woodward McCoach, Inc. 1180 McDermott Dr. West Chester, PA 19380
>610-692-9526 Ext. 102 ( Voice) 610-436-8258 (Fax)
>From: Ingraham, Andrew <[email protected]>
>To: '[email protected]' <[email protected]>
>Date: Tuesday, October 19, 1999 9:49 AM
>Subject: RE: [SI-LIST] : Thin Power Plane Dielectrics
> >Do these techniques use only different dimensions (perhaps with a higher
> >breakdown potential), or is the dielectric constant bigger as well?
> >I have seen warnings about "buried capacitance" layers that use high-Er
> >materials. While this is OK at lower frequencies, the advantage falls apart
> >at higher frequencies because the propagation delay through the buried
> >capacitance layer is more. Even though the capacitance per unit area is
> >large, the capacitance per nanosecond (risetime) may not be.
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