From: Jon Keeble ([email protected])
Date: Thu Dec 30 1999 - 14:18:14 PST
I hear that the cpi/cpci guys are looking at a new termination technique for
backplanes that supports more devices on the bus with the existing
I guess this involves parallel termination at both ends in Zo to Vt with Vt
close to the threshold region (?).
How much variation in Vt exists across the range of controllers, and across
the range of fpgas and cplds that people use for pci?
Hardware Engineering Manager
The bounds of Time, Space or Mechanics should never stand
in the way of a perfectly good idea.......
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