RE: [SI-LIST] : Data Sheet

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From: Bob Davis (bob@scsi.com)
Date: Fri Dec 24 1999 - 10:47:12 PST


Abe and The List;

We tried to get together a set of specifications for a standard electronic
form data sheet to include IBIS and other required data to do the SI and
other engineering requirements (Thermal, Shock, Physical Dimensions, Power
Requirements, etc). Basic stuff for electrical simulations and physical
modelling.

We had the party, as an IEEE project (P1537), and nobody came. The current
plan it to kill the project request at the Microprocessor Standards Commitee
meeting in January. We all want and need this stuff but nobody seems to want
to work on defining a standard method of definition and specificaton. The
IBIS group does not want to expand to cover it from what I have been able to
determine. Possibly ECIX will take on the task.

If anybody is interested in working on this project they should contact Lori
Mahoney (lmahoney@qdt.com).

Merry Christmas to All and have a Cool Yule.
May the New Millennium bring you properity and JOY.

Bob Davis
Consulting Engineer
Summit Computer Systems, Inc.

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Abe Riazi
Sent: Thursday, December 23, 1999 8:27 PM
To: 'si-list@silab.eng.sun.com'
Cc: Ken Hempen; Walt Otto
Subject: [SI-LIST] : Data Sheet

Dear Scholars:

   Like many other engineers, frequently I must refer to and review the
data sheets of various devices. While each part of a data sheet may
have some merits, there are certain sections with special significance
towards validating a behavioral model, as presented below.

   PINOUT
  The signal pin description section of a data sheet is frequently used
 to examine the completeness and accuracy of the pin mapping sections of
an IBIS model and also to determine various signal characteristics (i.e.
Input, Output only, I/O, synchronous, asynchronous, etc. ).

   VOLTAGE
   There are numerous voltage values specified in data sheet such as the
power rails, logic thresholds, the differential and the clamp voltages
that can be utilized for checking the corresponding voltage data present
in a behavioral model. We (meaning SI team at Anigma, Inc.) have
detected in some models erroneous voltage threshold values, which had to
be corrected because Vinh and Vinl can influence the level of ringback
violations and the flight time data which are obtained via simulation.

    CURRENT
    Current values IOH, and IOL (i.e. the source and sink output drive
currents) can prove useful for evaluating the driving strength of a
buffer model. To produce simulation results of optimum reliability, a
buffer model should behave neither weaker nor stronger than the actual
device.

     TEMPERATURE
     The operating temperature range of the device as specified in the
data sheet may be compared to the temperature range defined in the IBIIS
model for the three simulation corners (i.e. Min, Typ and Max ), to
determine if there is consistency.

   FREQUENCY
   The operating frequency range of a device, defined in the data sheet,
finds multiple applications towards verification and simulation of a
model. One interesting application of the frequency data is to allow
calculation of the rise time, usually not given in the data sheet, from
the relation:

    Rise Time = 5% to 20% of Clock Period.

   TECHNOLOGY
   Of course the logic family or technology of an IC (i.e. CMOS, TTL,
ECL, etc.) is a valuable information towards evaluating its buffer
model.
  The process technology, when present in the data sheet, is also
noteworthy.
   D.C. Sessions and Eric Bogatin have introduced the following useful
rule of thumb for determining the edge rate as a function of the process
technology:

    " Slow end of process results in approximately 100 ps rise time for
each 0.1 micron in channel length".

    For instance, when the device technology is 0.25 um the longest
expected risetime for the driver is about 250 ps.

    AC TIMING TEST LOAD
    The test load circuit defined by the semiconductor manufacturer for
measurement of propagation delay or output switching time of the device
is useful for checking the validity of Vmeas, Cref, Rref, Vref, defined
in some IBIS models and required for timing synchronization runs.
  To maintain clarity at this point; it is appropriate to consider an
example and the Intel 80960RN processor is well suited for this purpose.
 A PDF version of its data sheet is available at:

http://www.intel.com/design/iio/datashts/273157.htm

    The AC timing waveforms shown in section 4.6 (pp. 49 - 50) reveal a
measurement voltage of 1.5 V, and Figure 13 on Page 46 (section 4.7)
indicates that the PCI interface test conditions for this device consist
of:

   PCI Maximum AC specifications are tested with 50 pF load.
   PCI Minimum AC specifications are tested with a 0 pF load.

    Let us summarize the AC test load parameters for PCI signals,
provided by the data sheet:

    Vmeas = 1.5 V
    Cref = 50 pF (Maximum Specs)
    Cref = 0. pF (Minimum Specs)

   One implication of above values is that different test loads are
indicated for calibration of the Maximum, Typical and Minimum corner
models.
   It is interesting to look at the corresponding test load given in the
80960RN IBIS model (i960rn.ibs). Fortunately, this model is readily
obtainable:

http://www.intel.com/design/iio/smodels/index.htm

 The 80960RN IBIS model shows following test load parameters for
PCIIOBUF:

     Vmeas = 1.5
     Cref = 50 pF
     Rref=500 Ohms
     Vref = 0.0

   As you can see, the test loads defined by the data sheet and the IBIS
model are not identical, such being the case, it is the test load in the
data sheet which should be regarded superior and utilized in the
synchronization runs (for instance, TIME_TO_VM calibration of driver
models).

   PACKAGE
   The package style defined by the data sheet is applicable for
inspecting the package parasitics of the model. For 80960RN processor
the package type is 540-Lead H-PBGA as indicated by its data sheet.

   The package parasitic section for the i960rn.ibs consists of :

   [Package]
| typ min max
R_pkg 150m 81.5m 332.9m
L_pkg 12.0nH 5.7nH 22.5nH
C_pkg 2.00pF 1.80pF 2.20pF
|

Here, the important question to ask is:

 Are above parasitic values accurate for a 540-Lead H-PBGA package?

  To correctly answer such questions, it is helpful to collect and
analyze package parasitics for various types of IC packages.

   In addition to the data sheet elements described above, there are
several other parameters and guidelines which should be mentioned due to
their significant SI applications. They include, Tco, jitter, skew,
timing budgets, decoupling and routing recommendations found in some
data sheets (or supplementary technical documents). It is highly
desirable to be able to extract from the data sheet accurate values for
the input and output impedance; however, for all cases that I have
observed this can not be accomplished.

   In conclusion, pinout, voltage, current, temperature, AC timing test
load, and package style are among data sheet information that can be
directly utilized (i.e. no simulation required) towards qualification of
a behavioral model. Tco, skew, jitter, and timing budgets are also
important parameters; though the model needs to be simulated to
accurately evaluate their effects. The buffer model output impedance,
normally unobtainable from the data sheet, can be also ascertained by
means of simulation.

   Thanking you in advance for your valuable comments, wishing you all
joyous holidays and a very successful New year,

   Abe Riazi email: ariazi@anigma.com
ariazi@prodigy.net
   SI Engineer
   Anigma, Inc.
   1300 Valley Vista Drive
   Diamond Bar, CA 91765
   U.S.A.

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