From: [email protected]
Date: Wed Dec 22 1999 - 07:34:12 PST
I like your suggestion to start with a clean sheet of paper and ask
ourselves what should be done to optimize the I/O design.
In my experience working with computer system architects, they always want
more and more bandwidth, which in the past has meant more and more pins at
the boundary of an IC and more and more pins through connectors. And also
increased data rates. To combat the higher data rates (and associated
issues of noise, SSO, timing, ...) I have suggested to them to use
differential signalling. The complaint that I get back is that this takes
more pins. "I don't want to use two pins per signal when I can get twice
as many signals using single ended." they whine. Of course this isn't
really true since an increasing number of ground and power pins are
required, but system architects don't consider these since they don't show
up on any block diagram.
If it is really true that "Padrings are some of the most expensive real
estate around, so pin count should be minimized." then why don't we start
using each precious location on the padring to get more than one signal?
I'm suggesting keeping differential signalling to alleviate some of the SI
issues, but putting more than one logical signal on each differential pair.
With two logical signals per pair I'm back to the one signal to one wire
ratio that system architects love. See U.S. patent #5,872,813 "Dual
Differential and Binary Data Receiver Arrangement" as an example. Although
that patent refers to bipolar ECL-like circuits, I believe that some
similar concepts could be implemented in CMOS circuits.
The added complexity of the driver and receiver (and a little more power
due to increased voltage swing) may be worth it if we gain one or more
logical signals for each precious pin on the IC.
I'm not suggesting that "Dual Differential" should be an added requirement,
just that we consider somehow getting more that one logical signal onto
each pair of wires,
General Dynamics Information Systems
(Yes, GD does make computers, in addition to tanks,ships, and submarines)
With the year wrapping up and my inbox filling with
"Out of Office Autoresponse" messages, I thought I'd
kick off something more interesting than the joys of LVDS.
In particular, what would we use for signaling if we could
start with a totally clean sheet of paper? Rather than
immediately jump to a solution, I'm looking for some criteria:
* It has to be scalable. Given silicon technology trends, it
should migrate gracefully to lower-voltages and less
* It has to be SI clean. Output impedance should be matched
(stringency variable) to the line across the switching range.
Inputs switchpoints should be symmetrical and well-defined
(ie differential receivers). Power plane proliferation
leads to bad SI and wasted money, so separate termination
supplies are a Bad Thing.
* It has to be versatile. Single-ended, balanced single-ended, or
differential; multidrop or point-to-point; uni- or bidirectional;
all should be minor variations on the same system.
* It should be economical. Wasted power is a Bad Thing, so low
swing is a must. Padrings are some of the most expensive real
estate around, so pincount should be minimized. Line termination
can dominate a PWB so KISS is the rule. Power supplies (esp.
ones that can both sink and source current) are expensive and
nasty to deal with, so do without (both for termination and
funny analog functions in the I/O circuits.)
What can we add to the list? Remove? Priorities? (This is
engineering, we make tradeoffs.) Where does this take us?
-- D. C. Sessions [email protected]
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