From: D. C. Sessions ([email protected])
Date: Tue Dec 21 1999 - 13:08:07 PST
[email protected] wrote:
> > It's an operating-point thing. The transconductance of the input
> > devices isn't constant across the common-mode range.
> Ok... if it a safe generalization that the transconductance is going to more
> or less monotonically go down as the common mode voltage decreases, or is it
> still very much a function of the design of the input gates?
The NMOS is more or less monotonic, since the common-mode range doesn't
include the positive (3.3v) rail; the NMOS stage will hold flat or
increase slightly with increasing voltage. The PMOS devices will
increase gain for _lower_ voltage, or hold flat (design choice) down
to some limit. At that point, the PMOS devices, their load, or both
may go into their linear region (desaturate) with consequent loss of
transconductance, mode conversion, etc. How much of these effects
you actually get depends a LOT on design.
One thing for sure: unless you can tolerate a lot of receiver jitter,
you need to take this into account. Your silicon source probably
hasn't characterized the mode interactions on the data sheet, so it's
time to harass the Spice trolls.
-- D. C. Sessions [email protected]
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