RE: [SI-LIST] : Physcially-small far-end LVDS terminations?

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From: P.R.Dewasthalee (prdewa@wipinfo.soft.net)
Date: Sat Dec 18 1999 - 18:42:26 PST


Hi ALL,

For our application we are putting a R1-C-R2-R3 network to convert
logic levels and bias points across the "differential" logic families,
and also across voltages(5V to 3.3V), other than for such application,
I can't see why a cap be required.

Also a LVDS o/p is like a single phase full bridge inverter(well!?)
fed with a constant current source so it will need some path for
current to flow out of the HI pin and into the LOW pin, which is
effectively provided by the external resistor(s). The current is
in both AC/DC domains so presence of board impedence alone (100ohms )
between differential traces might not be sufficient.
Please correct, if I am missing something over here.

There is another point over here, which was sort of discussed here
on the list which is , WHAT IS DIFFERENTIAL SIGNALLING?
e.g.
CML/pCML have "both" the currents (diff. magnitude) sinking "into" the
differential pair.
ECL/pECL have "both" the currents (diff. magnitude) sourceing "out of"
the device.
LVDS fits into my concept of diffreential that the same magnitude current
flows in both the wires/tracks but in opposite direction.One sourcing
and other sinking.

I couldn't find the paper on Eric's (Bogatin Enterprises) website regarding
the Differential Signalling Theory(which I thought would seal the matter
once
for ever), hence this issue again.
Please pass me the link, if already posted on the site.

Thanks n regards,
- Dewa!
< P.R.Dewasthalee >
< prdewa@wipinfo.soft.net >

> -----Original Message-----
> From: owner-si-list@silab.eng.sun.com
> [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Jon Powell
> Sent: Saturday, December 18, 1999 10:39 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Physcially-small far-end LVDS terminations?
>
>
> Though I could easily be wrong, I don't believe that the below is
> true. My understanding of LVDS is that it requires ~100 ohm
> termination across the differential receiver in order to generate
> the required signal voltage.
>
> regards,
> jon
>
>
> Jim Freeman wrote:
>
> > Hi Eric,
> > Another answer would be to ensure that the differential
> impedance of the board between the differential pairs is 100
> ohms. Then you wouldn't need the resistors. I have performed
> Hspice sims on this and it works fine if the stackup/trace
> spacing is correct.
> >
> > Jim Freeman
> >
> > Eric Goodill wrote:
> >
> > > Hi,
> > >
> > > I want to use the typical LVDS termination where you have two
> 50-ohm resistors in series placed between the two lines of the
> LVDS diff. pair and also have a cap at the junction of the
> resistors to ground. I have a jillion LVDS pairs to terminate at
> a high-pin-count ASIC, and I'm looking to squeeze more
> terminations per square inch. (There's no hope of putting the
> terminations inside the ASIC at this point.) I'm hoping some
> company makes a single three-pin part the has those two resistors
> and a cap even if not specifically for termination use.
> > >
> > > How about any other ideas for even higher density?
> > >
> > > Regards, Eric
> > > --
> > > Eric Goodill
> > > Siara Systems, ericg@siara.com
> > >
> > > **** To unsubscribe from si-list: send e-mail to
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>
> --
> Jon Powell
> Director of HSSD Consulting Services
> Viewlogic Systems, INC.
> 805 988 8250
>
>
>
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