[SI-LIST] : Inner vs. Outer Layer Routing

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From: Chris Padilla (cpad@cisco.com)
Date: Fri Dec 17 1999 - 13:29:23 PST


More specifically, this is in regards to EMI and the use of
hi-speed differential signaling.

By hi-speed, I would say sub-nanosecond rise/fall times.

In terms of the likelihood to radiate (or be susceptable to),
it seems logical to me that microstrips would tend to radiate
more than (balanced) striplines. Looking at this single-ended,
it would seem true.

So the next question would be how does a differentially routed
signal help the cause to "justify" (to me) routing hi-speed
signals on outer layers rather than inner layers.

(Lets try and put off the SI implications of my thoughts here. I
know that signals travel faster on outer layers. I also know that
there is greater dispersion of the signal when placed on outer
layers. Lengths of traces are also important here, terminations,
vias, layer jumping, decoupling, etc., etc.) [Hmmm, now that I
write all those down, they may well be important!]

This leads me to ask exactly how much of a signal traveling down
this transmission line is differential-mode and how much is
common-mode? We know that radiation is often of the common-mode
variety.

Putting some numbers to this, let's assume 5-mil traces (w),
10-mil separation (s), and 4-mil dielectric height(s) (h). Is
trace height (t) an important factor here?

//////////////////////////////////////// Ground for stripline case
          5 10 5
         ____ ____
        |____|<---s---->|____| t
           h h
//////////////////////////////////////// Ground plane (infinite)

I have plans to run some very basic cases using Ansoft's HFSS--mostly
because that is what I am familiar with AND have access to. I am
posting this on the SI-LIST to gather any insightful thoughts on this
whole idea.

I have a feeling the overall answer to my question is: It depends!
It depends on components near the traces, vias, layer jumps, length
of the lines, environment these traces will be placed in (outside, in
a chassis, on a PC, etc.)

Thanks for your time.

Chris Padilla C i s c o S y s t e m s
EMC Engineer __________________________
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San Jose, CA 95134 | |
Email: cpad@cisco.com | | | |
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