RE: [SI-LIST] : Embedded Capacitance Project

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From: phelan, tony (phelan_tony@emc.com)
Date: Thu Dec 16 1999 - 12:09:22 PST


Would I get an answer to the following question if I attended the Workshop
or can someone short-circuit it for me and answer it here?
What is the effect on the capacitance derived from "Embedded Capacitance" if
there are a number of "cut-outs" - anti-pads from through-hole vias - in the
region of the power and ground pins of the device requiring decoupling?
Thanks
Tony

-----Original Message-----
From: Grasso, Charles (Chaz) [mailto:GrassC@LOUISVILLE.STORTEK.COM]
Sent: Thursday, December 16, 1999 12:58 PM
To: 'Signal Integrity'
Cc: Charbonneau, Richard A
Subject: [SI-LIST] : Embedded Capacitance Project

Hello,

Please find attached information regarding the NCMS Workshop
on Embedded Capacitance.

-----------------------------------------------

 <<EDC-FlierFeb2000.pdf>>
I have included the text below:
CONFERENCE DESCRIPTION: The development and use of Embedded Capacitance
Date: Feb 28-29th
Location: Tempe Arizona

Shelly, In case your Adobe still dies on you , I have added the
texr description below:

Text Description:
The Need:
The need for power-ground decoupling capacitance is nearly
universal in electronic circuits. Today, the solution to that
need is found in discrete chip capacitors. These devices
provide a wide range of capacitance values and many
excellent properties, such as stability over temperature and
frequency and reliability. However, use of discrete chip
capacitors also poses some fundamental problems - prob-lems
such as the significant cost of producing them in large
numbers and the amount of surface area they consume on
the circuit board. In addition, few designers or maintenance
engineers understand, with any rigor, how many decoupling
capacitors are truly required, how much capacitance they
should have, and where to locate them on the circuit.
In response to these inherent problems, and supported by
the findings of recent industry roadmaps, OEMs are now
viewing embedded passives technology as a promising
alternative to discrete passives in electronics manufacturing.
Embedding the capacitance in the circuit board frees up
space that can be used for other functions. The technology
may also improve performance and reliability by reducing
the number of solder joints and discrete capacitors, and
the associated failure modes. In addition, totalsystem cost
may also be lowered as a result of parts reduction and circuit integration.
However,efforts by one company - or even a small group of
companies - do not have high probability of success.
The case for a group effort was justified: the investigation
of multiple materials, with multiple fabricators,produces multiple chances
for success, with the efforts of each participant being highly leveraged.
The Project:
Recognizing the value of a collective solution, NCMS, together with more
than a
dozen partners, organized a collaborative effort aimed at advancing the
use of embedded capacitance technology for power supply decoupling.
The goal of the project was to encourage the development
and use of embedded capacitive materials in printed circuit boards. The
project team focused on the embedding of a single large (distributed)
capacitance within the circuit board. The team anticipates
that this capacitance will be utilized for power
supply decoupling.
Commercially available materials and developmental materials were evaluated
for
compatibility with the circuit board manufacturing
process, for materials properties, for reliability, and for
their ability to perform the decoupling function. The
project has thus taken some of the first steps towards the
realization of embedded passives in organic substrates.
Workshop Goal:
This workshop will provide a forum in which program
results can be disseminated to a targeted group of industry
representatives. Specifically, members of the project team
and NCMS's program manager will offer workshop
participants information and facilitated discussions on the
following: goals and objectives, test vehicle design, mate-rial
test results, reliability test results, electrical test results
(decoupling and EMI), and modeling of the electrical
performance of embedded distributed capacitance (EDC).
Why attend:
* Learn when, where, how to use these new EDC materials
* Learn from PWB fabricators technical know-how and
lessons learned
* Learn recommended design guidelines
* Receive workshop proceedings
* Receive project final report at 60% savings
Who should attend:
Individuals responsible for:
* PWB Fabrication
* PWB Design
* Electronic Products Designs
High-Speed Digital Designers
should NOT miss this workshop.
Development and Use of
Embedded Capacitance
Materials in Printed Circuit Boards
The Embedded Decoupling
Capacitance Consortium
Members
StorageTek
Delphi Delco
Electronics Systems
Raytheon Systems
3M Corporation
E.I. DuPont de
Nemours Co., Inc.
Litton Advanced
Circuitry
HADCO
Merix
National Institute of Stan-dards
and Technology
Penn State University
University of
Missouri - Rolla
National Center for
Manufacturing Sciences
Tobyhanna Army Depot
A Workshop
Conducted by:
The National Center for
Manufacturing Sciences
Embedded Decoupling
Capacitance Consortium
February
28-29, 2000
Fiesta Inn
Tempe, Arizona

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