From: D. C. Sessions ([email protected])
Date: Wed Dec 08 1999 - 15:50:48 PST
[email protected] wrote:
>
> Fabrizio and company,
>
> While I don't have any experience with model-to-hardware correlation at 1
> Gbit/s, I have done some work at slower speeds. I would be very leery of
> using a behavioral model at 1 Gbit/s. I was seeing 100-200 ps accuracy
> with the behavioral models I was using at slower speeds. (And I spent A
> LOT of time doing behavioral vs. SPICE vs. hardware correlation.) This
> could kill your design at 1 Gbit/s. I think you will find that "2nd and
> 3rd order" circuit behavior will suddenly become critical. The predrive
> stage and input waveforms will become significant as well as power and
> ground distribution.
>
> In fact, I would even be very critical of the SPICE models I am using at
> these speeds. In my opinion, any hardware running at this speed requires
> in-depth modeling and a well-designed component test bed to verify the
> accuracy of the modeling. Once the component is misbehaving in the system
> it's awfully hard to determine the cause of failure. Of course, this means
> you will have to limit the number of technologies you're running at this
> speed by the number of engineers who can characterize them!
Do you have a feel for how much of the discrepancy came from the active
device modeling and how much from interconnect? We *know* that IBIS is
inadequate for modeling parasitics, but it's not nearly so clear what
its limits are for active devices.
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