RE: [SI-LIST] : si-list test

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From: sweir (weirsp@a.crl.com)
Date: Wed Dec 01 1999 - 15:12:26 PST


Franck,

Unless you have a device with a defined and well controlled V-I curve that
matches the impedance of the transmission line, you will need to take some
measure to match the difference. Which termination method is most
desirable, ( or least obtrusive ) depends on your application.

Regards,

Steve.
At 05:30 PM 12/1/99 -0500, you wrote:
>Thanks for your answer. I think I missed the point. I have played with
>Hyperlink software, IBIS model and layer stackup. You create a line model
>with your parameters (drivers, receivers..), you simulate with LineSim, and
>you've got the results (rise/fall time behaviour). When you specifie, for
>example, a 50 ohms impedance, does-it mean you don't need any termination
>(serie or parallel) on that line ?
>
>-----Original Message-----
>From: Mike Mayer [mailto:Mike.Mayer@cp.artesyn.com]
>Sent: Wednesday, December 01, 1999 4:52 PM
>To: si-list@silab.eng.sun.com
>Subject: Re: [SI-LIST] : si-list test
>
>
> >>>>> "Franck" == Franck Thierry <franckt@eicon.com> writes:
>
> > Gentlemen, I have a basic question regarding SI. We're beginning
> > to control the impedance on our boards (due to the increase of
> > the clock frequency), but I have the following question: How do
> > you define the impedance ? It's not clear for me today where
> > this value is coming from. PCB designer said the IC vendors
> > shoud give me this information, IC vendors say to use a SI
> > software and to work with PCB designer, but I have to say I'm
> > lost in this. Maybe one of you could help me on that ?
>
>The impedance of a trace on your board is a function of the physical
>geometries of the trace and the properties of the board
>materials. Primarily it is the width and height above a plane for
>microstrips and the width and plane separation for striplines. There
>are application notes around that talk about it. For instance:
>
>http://www.fairchildsemi.com/an/AN/AN-661.pdf
>
>If you are using TTL or CMOS devices with rise times on the order of
>1nS or less (most modern parts) then you need all of the things people
>have told you -- the IC vendors give you models of their I/O buffers,
>and the SI software lets you simulate with the models. I would brush
>up on high speed design by looking into ssome of the more popular
>books on the subject. For instance:
>
>http://www.sigcon.com/books.htm
>
>If you can find the archives to this list there have been many threads
>on books.
>
>--
>============================================================================
>=
>Mike Mayer Artesyn Communication Products, Inc
>Senior Hardware Design Engineer Madison, WI
>Mike.Mayer@cp.artesyn.com http://www.artesyn.com/cp
>============================================================================
>=
>
>
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