From: Laurence Michaels (firstname.lastname@example.org)
Date: Wed Dec 01 1999 - 13:45:52 PST
Franck Thierry wrote:
> I have a basic question regarding SI. We're beginning to control the
> impedance on our boards (due to the increase of the clock frequency), but I
> have the following question: How do you define the impedance ? It's not
> clear for me today where this value is coming from. PCB designer said the IC
> vendors shoud give me this information, IC vendors say to use a SI software
> and to work with PCB designer, but I have to say I'm lost in this. Maybe one
> of you could help me on that ?
Well, depending on what exactly you ask, I could understand both of them
Figuring out the best value of impedance to ask the PCB vendors to match
requires information from many sources, including the IC designer (to
detailed enough driver and receiver models), and the PCB vendor (to find
out what possible impedances they can give, relative to trace width and
board cost), and some sort of SI tool (software or hardware prototype)
figure out how much different impedances affect your signal runs.
Figuring out the actual value of trace impedance from the layer stackup
is harder than it looks at first glance. Using textbook equations may
may not give you an accurate answer. The board vendors I've talked with
all say "You give us an impedance to match, and we tweak our process to
match it". You might be able to come close to what the vendors can
to, if you use the same impedance calculation tools and somehow get
"empirical results" book. Then again, maybe not.
Apparently, the dielectric constant of FR-4 (fiberglass resin composite)
isn't constant, and depends on the ratio of glass fibers to resin, the
amount of pressure applied during processing, the actual manufacturer of
the glass fabric and resin, and several other factors that vary from
vendor to vendor. I've heard that the possible variation is 3.8-4.5 for
certain vendors, but I'm not certain of that number. Also, traces do
necessarily have a rectangular cross-section, which will effect the
calculations of impedance.
It seems to be a non-trivial problem (at least with these vendors) to
come up with a standard impedance controlled stackup that all vendors
can make. Given the same impedance requirements and basic stackup, some
say "OK, if you can make traces X mils on layer 1, with the following
stackup", some have X larger, some smaller, and one says "We can't
possibly do that".
I may be going about this the wrong way, but it seems impossible to
get one stackup that all vendors can build a controlled impedance board
with. Has anybody had any luck with this?
-- Laurence Michaels
**** To unsubscribe from si-list: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:03 PST