From: Jim Freeman ([email protected])
Date: Mon Nov 29 1999 - 12:44:00 PST
I believe that the capacitance is directly under the metal pad itself. This could be done with a metal stacking and various connections under the pad.
> One thing to remember about gate oxide capacitance -- the bottom
> plate of the capacitor is the FET channel which is fairly resistive.
> So, especially for caps formed from relatively long devices, there
> can be substantial ESR. This effect does not show up in SPICE
> models using MOS devices with shorted drain and source. Capacitors
> made of shorter channel devices have lower series resistance, but
> they're less area efficient.
> Mike Jenkins Phone: 408.433.7901 _____
> LSI Logic Corp, ms/G715 Fax: 408.433.7461 LSI|LOGIC| (R)
> 1525 McCarthy Blvd. mailto:[email protected] | |
> Milpitas, CA 95035 http://www.lsilogic.com |_____|
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