From: [email protected]
Date: Tue Nov 23 1999 - 15:14:18 PST
DC's comment reminded me an instance a while ago. A colleague
of mine came to me to talk about the characterisation results of an
ethernet chip and asked about the output waveforms of some IO
pins, which looked slow to him.
him: Is that your intentional design?
me: Well, it looks a little bit slow yet it will fit into the lower end of
I knew exactly what he felt. We would like to put our typical design
target at the middle of the spec. range that you are much safe to avoid
troubles of any unforeseen factors. Perhaps I was a bit more
concerned to SI issues at board level in trading with our usual
safety guard. Thanks to the subscription to this forum :-).
Anyway, it is a good point to push marketing guys to think about
the Philips' approach.
---------------------- Forwarded by Raymond Leung/QSA/AU on 24/11/99 08:54
"D. C. Sessions" <[email protected]> on 24/11/99 07:05:46
Please respond to [email protected]
To: [email protected]
cc: (bcc: Raymond Leung/QSA/AU)
Subject: Re: [SI-LIST] : si-list crash addendum
Adrian Shiner wrote:
> I'll second that. Irrespective of the immediate personal need, it is a good
> forum. I also second the many requests to suppress the adverts for
> employment opportunities in particular..of no value to me and wasting my
> money. We residents of the UK are still getting S*****D to access the
IMHO a www-page with (weekly?) digest of links to this forum would
be a good compromise. Employers could post to the "board" and the
digest would direct people to new postings.
> Anyone working on slowing switching time in ICs where they are not
> absolutely necessary? You chip designers and fabricators are strangely quiet
> on this subject. Surely you are not playing the olld "CAVEAT EMPTOR" game?
> If you are, then shame on you.
[Speaking for Philips]
Last week we had a meeting of the corporate SI&EMC community.
The main emphasis is that Philips' primary tool for limiting
SI & EMC problems is edge-rate control; our standard libraries
have 5000, 10000, and 20000-ps edge time parts.
[Speaking for DCS]
... which causes quite a bit of trouble when my customers are
exclusively interested in system cycle times under 3000 ps.
My job is solving my customers' problems, and the solution
MUST begin with them.
[Speaking for the semi manufacturers]
[Yeah, right, Intel is gonna let me speak for THEM???]
It's a supply-and-demand problem. We *know* we have customers
who will pay for let-it-all-hang-out speed. They get taken
care of. If there's a demand (as in pounds, francs, Deutschmarks,
lira, guilders, etc.) then we'll be more than happy to fill it.
Money talks, and if you don't ask you won't receive.
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