Re: [SI-LIST] : Re: IBIS datasheets for PCI and DDR

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From: D. C. Sessions (dc.sessions@vlsi.com)
Date: Tue Nov 23 1999 - 12:48:24 PST


Adrian Shiner wrote:
>
> This makes one wonder how on earth the IC designers/manufacturers are
> working. Product "not fit for purpose" (UK law concept) springs to mind at
> the IC level.
>
> Who is active on the ISO committees? That is where the future lies for
> standardization.

The ISO has nothing to do with this. It's strictly a JEDEC operation.
Although JEDEC is part of EIA, which is an ISO body, the signaling and
memory specs are not proposed for ISO standardization. Partly because
the ISO process is so slow that a part would be obsolete before the
standard ever saw daylight.

In any case, the rise and fall times _are_ specified. The electrical
details are in SSTL-2, which specifies a 1v/ns slew rate for characterization.
Manufacturers are of course allowed to go faster, but they can't use
that extra speed to make up for other shortfalls.

> ----- Original Message -----
> From: <gedlund@us.ibm.com>
> To: <si-list@silab.eng.sun.com>
> Sent: 23 November 1999 14:46
> Subject: Re: [SI-LIST] : Re: IBIS datasheets for PCI and DDR
>
> > Thanks, DC. Are you working on the DDR committee? I was looking at the
> > spec the other day, and I noticed there was a really nice capacitance
> spec,
> > some IV curves, but no rise/fall times, which makes it hard to create a
> > behavioral model that's consistent with the spec. What's your take? Has
> > anyone proposed adding edge rates?
> >
> > Greg Edlund
> > Advisory Engineer, Critical Net Analysis
> > IBM
> > 3650 Hwy. 52 N, Dept. HDC
> > Rochester, MN 55901
> > gedlund@us.ibm.com
> >
> >
> >
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-- 
D. C. Sessions
dc.sessions@vlsi.com

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