RE: [SI-LIST] : SDRAM termination

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From: Chris Cheng (hycheng@3pardata.com)
Date: Fri Nov 19 1999 - 11:32:35 PST


both ti and idt has sdram address buffer with built in series
terminator.
check out
http://www.idt.com/docs/74ALVC162831_DS_35237.pdf for spec

and http://www.idt.com/products/pages/Logic_HSPICE.html for spice model.

chris
> -----Original Message-----
> From: owner-si-list@silab.eng.sun.com
> [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Mike Mayer
> Sent: Friday, November 19, 1999 6:48 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : SDRAM termination
>
>
> >>>>> "david" == david gil donate <dgd@dimat.es> writes:
>
> > Hi, We have designed a SDRAM board with Micron chips. We have
> > terminated with a serie resistor all the data lines but we
> > haven't done it with the adress line because we don't see it in
> > others SDRAMs boards. Now we have too much si problems with the
> > adress lines. We have used Hyundai chips and we haven't had this
> > si problems and our board runs OK. Do you think that we should
> > terminate the adress lines in the SDRAM board too?
>
> In general, it will be necessary to terminate the address lines. As
> someone else mentioned, there are buffers available that incorporate a
> sereis termination resistance. Depending on the topology of your nets,
> you have to account for the fact that you are using reflected wave
> switching (i.e., the longest delay is at the part closest to the
> driver) when you do a timing analysis.
>
> --
> ==================================================================
> ===========
> Mike Mayer Artesyn Communication
> Products, Inc
> Senior Hardware Design Engineer Madison, WI
> Mike.Mayer@cp.artesyn.com http://www.artesyn.com/cp
> ==================================================================
> ===========
>
>
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