From: [email protected]
Date: Fri Nov 19 1999 - 06:58:58 PST
David,
The series termination of an address line on a buffered DIMM (I'm assuming
buffered from your note) is dependent on several things: buffer output
impedance, etch impedance, net topology (the order you route the SDRAMs),
and the capacitance of the address inputs on the SDRAM. You may be seeing
vendor-to-vendor variation in input capacitance. You can measure pin
capacitance pretty easily with a TDR. (see
www.hp.com/hpj/apr96/ap96a11.htm). Sometimes you may not need any series
termination at all, e.g. in the case of a stacked DIMM where the loading is
very heavy.
I would recommend getting a good model for the buffer and the SDRAM(s) and
go to work on some simulations. Play around with the net topology, series
resistance, and load capacitance and see if you can discover the
sensitivities of your net. Ask your vendors if they can prove to you that
the models accurately represent the silicon. You may not like the answer!
Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email protected]
david gil donate <[email protected]> on 11/19/99 04:45:07 AM
Please respond to [email protected]
To: "Si-List (Correo electr�nico)" <[email protected]>
cc:
Subject: [SI-LIST] : SDRAM termination
Hi,
We have designed a SDRAM board with Micron chips. We have terminated with a
serie resistor all the data lines but we haven't done it with the adress
line because we don't see it in others SDRAMs boards. Now we have too much
si problems with the adress lines. We have used Hyundai chips and we
haven't had this si problems and our board runs OK.
Do you think that we should terminate the adress lines in the SDRAM board
too?
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