From: Greim, Michael ([email protected])
Date: Fri Nov 19 1999 - 04:38:45 PST
From the sound of things, there wasn't any simulation done
on this, so I will start from that assumption. On the data
lines, did you perform termination at both ends of the net,
and if not, which end and why as this is a bidirectional net
and I assume that this is not write only memory 8-). What
can you tell us about the stackup of the board and what the
net topology is? If I had to take a wild guess at this point,
I might suspect the address or the controls/clock. You might
want to take a look at this. As these are unidirectional and
perhaps one load nets, you might want to attempt to terminate
at the load with a resistor network pack. This should be easy
to try in the lab. Have you checked the interface lines with
a scope yet? What do they look like? Your description is at
to high a level to solve right now.
The bounds of Time, Space or Mechanics should never stand
in the way of a perfectly good idea.......
The time is gone, The email's over, thought I'd
something more to say.........
Michael C. Greim Consulting Engineer
Mercury Computer Systems, Inc email: [email protected]
199 Riverneck Road V: 978-256-0052/x1607
Chelmsford, MA 01824-2820 F: 978-256-4778
> -----Original Message-----
> From: david gil donate [SMTP:[email protected]]
> Sent: Friday, November 19, 1999 5:45 AM
> To: "Si-List (Correo electrónico)"
> Subject: [SI-LIST] : SDRAM termination
> We have designed a SDRAM board with Micron chips. We have terminated with
> a serie resistor all the data lines but we haven't done it with the adress
> line because we don't see it in others SDRAMs boards. Now we have too much
> si problems with the adress lines. We have used Hyundai chips and we
> haven't had this si problems and our board runs OK.
> Do you think that we should terminate the adress lines in the SDRAM board
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