Re: [SI-LIST] : how to best validate edge rate and output impedance

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From: Dr. Edward P. Sayre (esayre@nesa.com)
Date: Thu Nov 18 1999 - 13:33:51 PST


Pat:

Please communicate your concerns to the IBIS accuracy folks, Bob Haller of
Compaq and Greq Edlund at IBM in Rochester. These are exactly the kind of
questions the IBIS Accuracy Specification is meant to address.

ed Sayre
Chairman, IBIS Users' Group
====================================
At 02:31 PM 11/17/99 -0600, Pat Zabinski wrote:
>
>We are having "conversations" with a vendor of macro libraries
>about how to specify/validate two key parameters for output buffers:
>1) output impedance; and 2) edge rate (full-swing, rail-to-rail
>CMOS).
>
>We have clearly specified these values, but we failed to specify
>how these values are determined (oops!). The approach we typically use
>produces much different results than the vendor uses, and I'm
>interested in getting input from folks on any "industry standard"
>or "best engineering" approach you use.
>
>For output impedance:
>
> * we validate by running a full spice simulation with
> the buffer driving an ideal transmission line and tweaking
> the line's impedance until we obtain proper waveforms
>
> * the vendor uses DC I-V curves to design the output
> impedance and stops there
>
> (for this particular project, their values are about
> 10-15% higher than ours)
>
>For edge rate:
>
> * we validate by simulating an output buffer driving an
> ideal transmission line terminated with an input buffer;
> we then measure the 20-80% edge rates at the far end.
>
> * the vendor places a lumped capacitor load directly on
> the output of the buffer and measures the edges (I'm
> not sure what %'s they use).
>
> (for this project, their edge rates are 3X-longer/slower
> than what we obtain!)
>
>Is anyone aware of industry-standards for characterizing these
>values (in simulation, not measurement)? Outside of standards,
>does anyone have a particular approach they like to use?
>
>Thanks for the input,
>Pat
>
>
>
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