RE: [SI-LIST] : Transient impedance--IBIS models

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From: Muranyi, Arpad ([email protected])
Date: Thu Nov 18 1999 - 09:45:30 PST


I will attempt to answer your question on feedback and Cdg quickly.

The effects of the parasitic capacitance of the output transistor is
included in
the Vt curves (when the buffer is driving) and in C_comp (when the buffer is

A prime example for this is the small bump in the Vt curve that precedes the
edge going in the opposite direction. This bump is a result of the gate
bleeding onto the drain while the gate voltage is less than the threshold
of the output transistor (Vth). The output transistor has a fairly high
when its gate voltage is below Vth, therefore the Cdg capacitance can couple
waveform from of the gate to drain easily. When the transistor starts
turning on,
its impedance goes low, and the drain voltage starts going the right
The coupling effects of the Cdg capacitance are still there, but only in
down the edge somewhat. All of this is true for P-channel pullups and

For N-channel pullups you will not see this, because the gate to drain
is not inverting. In fact, you might observe a small initial "drive" before
real edge starts, again, doe to the capacitive coupling of the gate waveform
drain. In this case the gate voltage helps the edge, and may speed it up

When the buffer is 3-stated, the transistor channels are high impedance, the
gate voltages are steady. So the Cdg capacitance will look like an
Cds, which is (or supposed to be) included in the IBIS C_comp value.

I am just wondering, why do you ask "how does one measure the effect of
within the output"? Do you want to "measure" this effect separately because
want to know the value of the Cdg capacitor for some reason? Or do you just
to know whether this effect is modeled correctly in the IBIS model?

I don't know if you are interested in other types of feedback, but in
IBIS does not address feedback buffers in a true sense. IBIS can model the
so-called "bus-hold" buffers which work based on feedback, but it doesn't
the timing related response completely. This, however, is not because it
be done. It just was not implemented yet, because no one came forward with
the need
and behavioral description methodology yet.

I hope this will answer your questions.

Arpad Muranyi
Intel Corporation

-----Original Message-----
From: Chuck Hill [mailto:[email protected]]
Sent: Wednesday, November 17, 1999 6:59 PM
To: [email protected]; '[email protected]'
Subject: RE: [SI-LIST] : Transient impedance--IBIS models


You're right. I looked at your slides on the IBIS modeling presentation.
If one does the measurements right, and creates correct V-t tables, the
output impedance through the switching interval can be higher. The problem
I encountered was a poor method of creating an IBIS model.

On a related issue, how does one measure the effect of feedback within the
output? For example, a gate to drain capacitor. I guess this falls in the
"slew rate controlled" output arena. So how does IBIS account for these
effects and how could one measure an output driver with these
characteristics and create an IBIS model?

Charles Hill, consultant

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