Re: [SI-LIST] : Question : differential LVPECL test headers

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From: sweir (weirsp@a.crl.com)
Date: Tue Nov 16 1999 - 21:38:01 PST


Bruce,

Howard speaks the truth. Assuming that you do not need to go directly into
a logic analyzer, decouple the stub from your test connector, and
associated traces with an adequate resistance, and then parallel terminate
the result. The penalty in signal loss will be more than made up for in
saved grief.

Regards,

Steve.
At 10:17 PM 11/16/99 -0500, you wrote:

>I have to provide test points for a 16-bit parallel datapath,
>which are all single-ended LVPECL. The bus is synchronous,
>and associated clocks and control are differential LVPECL, and
>signals are 155 MHz, typical of SONET/SDH.
>
>The test points would ideally be headers of some sort, but
>signal integrity is a priority. It makes me nervous to route
>the signals across the board to convenient test headers.
>Is there a technique for doing this, or should I employ a
>conservative approach?
>I have been browsing Howard Johnson's book, High-Speed Digital Design,
>and am aware of the section on "Embedded fixtures for Probing" p.103
>
>Is this technique suitable for LVPECL, either single-ended
>or differential? I have observed differential signals before,
>but they were slow in comparison to these speeds. What special
>considerations are there for observing high-speed differential
>signals?
>
>Regards,
>
>Bruce
>
>
>Bruce Rosenquist, Designer
>DesignPRO Inc.
>35 Stafford Rd., Unit 1
>Nepean, Ontario
>K2H 8V8 CANADA
>
>http://www.designpro.org
>
>brosen@designpro.org
>
>
>
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