From: Paul Levin ([email protected])
Date: Wed Jun 06 2001 - 15:23:32 PDT
-------- Original Message --------
Subject: Re: [SI-LIST] : Multiple PLL's in series
Date: Wed, 06 Jun 2001 15:21:33 -0700
From: Paul Levin <[email protected]>
To: Aaron Frank <[email protected]>
References: <[email protected]>
First of all, you must consider a phase-locked loop as a cross-over
for jitter characteristics. Up to roughly the loop bandwidth, the PLL
the frequency and jitter characteristics of the incoming signal. Beyond
loop bandwidth, the PLL delivers the free-running jitter characteristics
local voltage controlled oscillator. At the loop bandwidth frequency
some jitter peaking, i.e., more comes out than was present in either the
or the voltage controlled oscillator. (That's the beauty of dividing by
It sounds like you are planning to cascade "identical" phase-locked
so, you will discover that while the regions above and below the loop
remain reasonably constant from output 1 to output 32, the jitter around
bandwidth will climb as you move down the chain.
In the meantime, might I suggest that you get ahold of "Frequency
Design Handbook" by James A. Crawford (Artech House, 1994) and study
the excellent chapter on Phase Noise.
Senior Principal Engineer
Aaron Frank wrote:
> Re: Multiple PLL's in series
> Has anybody had experience putting PLL's in series?
> I have a need to put chips in series, each of which feeds a high-speed clock
> signal (and data) to the next chip in the chain (source synchronous data
> clocking). The clock signal is received by the next chip, PLL locked, and the
> PLL'd version of the clock is fed to the next device. This goes on for 32 chips
> in series. The clock frequencies I am dealing with are 100MHz and 200MHz.
> Understanding that PLLs have short-term jitter specs (cycle-to-cycle) as well
> as long-term jitter specs (phase error), I belive that the short-term jitter
> will not accummulate from device to device. My concerns are:
> 1) Each chip will add it's own long-term phase error, changing the duty cycle
> of the clock. This means that I cannot use the clock for anything which
> requires a controlled duty cycle (ie: 40-60%).
> 2) Since the control transfer function of PLLs often has a positive gain "peak"
> in it's feedback path, putting 32 devices in series could result in a large
> positive gain component, and the overall structure would be unstable.
> Any insight into this design challenge would be appreciated?
> Alternatively, any mention of available resources which may be beneficial would
> also be appreciated.
> Thanks in advance,
> Aaron Frank, P.Eng
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