[SI-LIST] : Multiple PLL's in series

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From: Aaron Frank (aaron@sibercore.com)
Date: Wed Jun 06 2001 - 14:02:28 PDT


Re: Multiple PLL's in series

Has anybody had experience putting PLL's in series?

I have a need to put chips in series, each of which feeds a high-speed clock
signal (and data) to the next chip in the chain (source synchronous data
clocking). The clock signal is received by the next chip, PLL locked, and the
PLL'd version of the clock is fed to the next device. This goes on for 32 chips
in series. The clock frequencies I am dealing with are 100MHz and 200MHz.

Understanding that PLLs have short-term jitter specs (cycle-to-cycle) as well
as long-term jitter specs (phase error), I belive that the short-term jitter
will not accummulate from device to device. My concerns are:

1) Each chip will add it's own long-term phase error, changing the duty cycle
of the clock. This means that I cannot use the clock for anything which
requires a controlled duty cycle (ie: 40-60%).

2) Since the control transfer function of PLLs often has a positive gain "peak"
in it's feedback path, putting 32 devices in series could result in a large
positive gain component, and the overall structure would be unstable.

Any insight into this design challenge would be appreciated?
Alternatively, any mention of available resources which may be beneficial would
also be appreciated.

Thanks in advance,
Aaron Frank, P.Eng

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