Re: [SI-LIST] : MECL System Design Handbook

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From: Scott McMorrow (scott@vasthorizons.com)
Date: Wed Jun 06 2001 - 10:32:23 PDT


Ken,

I haven't looked at the effects of the different modes, and the literature
I have is pretty sparce on the matter. We'll be looking at the issue in more
depth as time goes on, and I'll probably have my electromagnetics expert, Rob
Hinz, do a better mathematical analysis than I am capable. ( I am generally just a poor
old intuitive engineer.)

As for whether the corner becomes an issue, it depends upon margins, doesn't it.

For example, if one is using serpentined traces for clock matching, and there
is a different number of corners on one trace relative to another, the little 1 to 5 ohm
reflection will cause loss. That loss will cause a change in delay. Now, the delay will
be quite low ... maybe in the 1 to several picosecond range. For a design like the
"silly" Rambus, these types of delays actually do make a difference. We were compensating
for the stub length effect of vias traversing different layers, and compensating for
traces on different dielectric layers. When the total skew budget is less than 100ps,
everything matters.

If one is designing a board to a +/- 10 ohm impedance tolerance and has performed
rigorous worst case analysis to show that on a particular bus a board will "just" work
at the worst PVT point, and the bus were sufficiently fast to have edges which caused
some reflection at the corners, then I think that a little corner might cause a difference.
Will it alone cause a design failure ... probably not. But, it along with the many other
unaccounted effects on the board will. (Murphy always wins in the end.)

But ... if one is designing high speed differential interface, one might want to look at the
loss of a corner and compare it to the loss of the trace.

For corners I calculate the transmission loss to be the following:

S12@ 5GHz = -0.069 dB
S12@ 15GHz = -0.279 dB
S12@ 20GHz = -0.397 dB

For 5-mil stripline traces I calculated the loss per inch due to dielectric loss and skin effect
for different materials at different frequencies. YMMV:

 Attenuation per inch in dB of a 5 mil, 50 ohm microstrip trace.

                5GHz 10GHz 20GHz
FR4 -0.84 -1.59 -3.07
Fr406 -0.42 -0.75 -1.39
G200 -0.32 -0.55 -0.99
RO4350 -0.22 -0.35 -0.60
RO4003 -0.19 -0.30 -0.49

Corner -0.069 -0.279 -0.397

Ratio of trace loss per inch to corner loss for 5 mil 50 ohm stripline.
(how many corners does it take with a 5 mil trace to equal
the loss of the trace per inch?)
                5GHz 10GHz 20GHz
FR4 12 5.7 8
Fr406 6 2.7 3.4
G200 4.6 2 2.5
RO4350 3.2 1.25 1.5
RO4003 2.75 1 1.25

Ratio of corner loss to trace loss for 5 mil 50 ohm stripline.
(How many inches of trace is a corner equal to?)
                5GHz 10GHz 20GHz
FR4 0.083 0.175 0.125
Fr406 0.166 0.370 0.294
G200 0.217 0.500 0.400
RO4350 0.312 0.800 0.666
RO4003 0.363 1.000 0.800

Lets look at a 2.5 GBPS data stream.
The first harmonic of the data stream is 1.25 GHz.
The third harmonic is 3.75 GHz,
The fifth harmonic is 6.25 GHz.
For all of these harmonics, the loss due to a corner is small
compared to the loss of an inch of FR4. Even for low loss
material, one corner is equivalent to less than .3 inches of
trace. One might want to limit the number of corners for
long trace lengths in low loss material, to increase the design
margin or to increase the maximum end to end length
allowable.

For a 10 GBPS data stream:
The first harmonic is 5 GHz,
The third harmonic is 15 GHz,
The fifth harmonic is 25 GHz.

Again, for high loss materials like FR4, the loss due to one
corner is 10 times smaller than the loss due to an inch of trace.
But, if you need to use low loss materials at this data rate,
and most likely you do, then a corner is a significant effect
that should be accounted for. Removal of a corner or
optimal corner chamfering can increase design margin or
allow for nearly an additional inch of trace per corner. (To me, this
is a fairly good cost/benefit ratio.)

At 40 GBPS the first harmonic is 20 MHz.
Everything matters.

best regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

> Scott,I was mathematically looking at what happens with modes at a bend, and assumed that superposition held. When I add > reflection coefficents from the TE and TM portions I get (for my geometries) about -23 dB, or a Zo delta of about 5 to 6 ohms (47 > ohms to 41 ohms), indicating not much effect. No frequency effects, just geometric. I will do frequency effects some time today > if I get the time. Then I stumbled across a section in the text I'm using about longitudinal wave issues at approx. 10 GHz, and > will delve into that next. What's your understanding of when the corner can become an issue, modes + longitudinal?Ken > -----Original Message----- > From: owner-si-list@silab.eng.sun.com [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Scott McMorrow > Sent: Tuesday, June 05, 2001 6:04 PM > To: si-list@silab.eng.sun.com > Subject: Re: [SI-LIST] : MECL System Design Handbook > Lee, > > As to whether a corner discontinuity for a "realistic" trace can be > measured with a TDR, the answer to this question is closed. > > It can. > > Whether the "effect" matters is a different animal altogether > and depends upon the application and the margins within a > particular design. > > Gus Panella of Molex and myself have provided a preliminary > paper to the si-list on the "perturbations" of right angle bends and measurement > of same with a TDR. These measurements of 12.5 mil low loss stripline > traces are consistent with Tom Dagostino's experience. A number of > days back, I copied you on this paper. > > With the impedance of a trace held as a constant, the discontinuity seen by an > edge passing a corner should remain consistent across a very wide range > of trace widths. Why? Because the important dimension W/h remains > constant with size scaling. Since W/h is constant (to achieve the same impedance) > Eeff is also constant. With Eeff constant for varying trace widths (and associated > adjustment of the trace height above the plane for impedance) the trace velocity will be > identical. > Since the trace velocity is identical, the distributed L and C is exactly the > same for any length of trace or size of feature. This means that as the > trace width, corner, and trace height above the plane are scaled geometrically. > the effect of the corner discontinuity remains the same. > > Now, there are limits to this analysis. > > 1) TEM mode propagation is assumed. > 2) Corner feature length is less 1/10 risetime. > > As the trace width decreases, there is also a different limit. Skin effect losses > will eventually attenuate the edge harmonics and limit the risetime that > reaches the corner. But, when this is the case, we really aren't transmitting > any really interesting signals anyway. > > > regards, > > scott > > -- > Scott McMorrow > Principal Engineer > SiQual, Signal Quality Engineering > 18735 SW Boones Ferry Road > Tualatin, OR 97062-3090 > (503) 885-1231 > http://www.siqual.com > > Ritchey Lee wrote: > >> TOm, >> >> I have such PCBs and have launched edges as fast as 60 pSEC into them with no detectable perterbation. My objective is to see >> how PCB features affect logic signals, none of which have edges faster than 60 pSEC by the time they reach the PCB. All of us >> who are looked to for technical guidance should be doing the same. >> >> It might be possible to "see" a 90 corner at some very high frequency, some use numbers like 40 GHz, or at some bery large >> geometry, like 100 mil wide traces, but these cases aren't germain to what our community works with day to day. The stuff of 10 >> mil traces ans thinner and edges of 60 pSEC and slower are of interest. That's the reagon where we should be sure our advice >> has meaning. >> >> Lee >> >> Dagostino, Tom wrote: >> >> > I agree that this board is not the latest technology, that is why I qualified my offer, but it does have real square corners >> > and the traces of interest are fairly isolated. If you can send me a test board that has good square corners that are isolated >> > and that I can get a clean launch into I will measure that and publish those results too.I now have the GPIB system working on >> > my scope again and will make some measurements on the test board I have. Tom Dagostino >> > Modeling Manager >> > Mentor Graphics Corp. >> > SAE >> > tom_dagostino@mentor.com >> > 503-685-1613 >> > >> > -----Original Message----- >> > From: Ritchey Lee [mailto:leeritchey@earthlink.net] >> > Sent: Friday, June 01, 2001 10:10 AM >> > To: Dagostino, Tom >> > Cc: 'Dr. Edward P. Sayre'; Rich Peyton; Roehrner Wolfgang; si-list@silab.eng.sun.com >> > Subject: Re: [SI-LIST] : MECL System Design Handbook >> > Wolfgang, >> > >> > The test board you cite doesn't relfect how real logic PCBs are built. No one uses 100 mil wide traces. Also, no >> > one builds PCBs with such thick dielectrics. It would be misleading to suggest that what you measure with the >> > structures you have apply to the structures that appear in logic PCBs, unless you show that the scaling is >> > appropriate. >> > >> > Lee >> > >> > Dagostino, Tom wrote: >> > >> > > >> > > >> > > I have a board that demostrates this very nicely. As soon as I get my scope/extraction system working again I will >> > > publish some results. The board is two layers with ground on one side and 50 Ohm traces on the other. Yes, these >> > > traces are quite wide, on the order of 0.100". There are several right angel bends with square corners. The >> > > corners are quite visible. >> > > >> > > Tom Dagostino >> > > Modeling Manger >> > > Mentor Graphics Corp. >> > > SAE >> > > tom_dagostino@mentor.com >> > > 503-685-1613 >> > > >> > > -----Original Message----- >> > > From: Dr. Edward P. Sayre [mailto:esayre@nesa.com] >> > > Sent: Thursday, May 17, 2001 6:47 PM >> > > To: Ritchey Lee; Rich Peyton >> > > Cc: Roehrner Wolfgang; si-list@silab.eng.sun.com >> > > Subject: Re: [SI-LIST] : MECL System Design Handbook >> > > >> > > Lee and others: >> > > >> > > I don't know what kind of TDR or fixturing you might have used, but the >> > > excess capacitance is very real and can be seen. It is also illustrated in >> > > a number of microwave books. If your fixturing caused a significant loss (> >> > > 100 ps) of risetime of the step out of the TDR, then the capacitance effect >> > > will be washed out. >> > > >> > > Sincerely, >> > > >> > > ed sayre >> > > ========================== >> > > At 08:36 AM 5/10/01 -0700, Ritchey Lee wrote: >> > > >Any of you who want to know how the myth about right angle bends got >> > > >started, look >> > > >at figure 7.17 on page 155. This alleges that right angle bends can be >> > > >seen by a >> > > >TDR. I've done this measurement dozens of times and coiuld never see a right >> > > >angle bend. >> > > > >> > > >A few years ago, I called Mr. Blood the author of the book and asked >> > > >about the >> > > >diagram. His reply was that he knew the diagram was flawed, but there >> > > >wasn't time >> > > >to fix it before the book went to press. >> > > > >> > > >As a result, thousands of engineers have spend countless time worrying >> > > >about right >> > > >angle bends. >> > > > >> > > >When we publish technical information such as this, it is important to >> > > >insure it >> > > >is accurate. >> > > >This applies especially to applications notes, whic often contain entirely >> > > >false >> > > >data. >> > > > >> > > >Lee >> > > > >> > > >Rich Peyton wrote: >> > > > >> > > > > FYI, >> > > > > >> > > > > The hard copy can be ordered free of charge. >> > > > > >> > > > > Rich >> > > > > >> > > > > Roehrner Wolfgang wrote: >> > > > > >> > > > > > http://www.onsemi.com/home <http://www.onsemi.com/home> >> > > > > > >> > > > > > In the Menu-tree go to: >> > > > > > >> > > > > > Technical Documents >> > > > > > CD/Document Ordering >> > > > > > General Search >> > > > > > >> > > > > > search for document number: hb205 >> > > > > > download it as pdf (or order!). >> > > > > > >> > > > > > regards, >> > > > > > Wolfgang >> > > > > > >> > > > > > -----Original Message----- >> > > > > > From: Ashok Babu K [mailto:k.ashokbabu@gdatech.co.in] >> > > > > > Sent: Tuesday, April 10, 2001 12:39 PM >> > > > > > To: si-list@silab.eng.sun.com >> > > > > > Subject: [SI-LIST] : MECL System Design Handbook >> > > > > > >> > > > > > Hi all, >> > > > > > I see that a good resource for general high speed termination design and >> > > > > > especially ECL/PECL termination is Motorola's MECL System Design >> > > > Handbook by >> > > > > > Blood Jr., and William R. Many articles and papers specify the same as a >> > > > > > good resource. Unfortunately I could not get the soft copy of the MECL >> > > > > > System Design Handbook. I could not get it from the ON Semiconductor >> > > > > > website. If any of you have the PDF file of the same or know where it >> > > > can be >> > > > > > obtained, please inform me. Any suggestions of other resources are highly >> > > > > > welcome. >> > > > > > Regards, >> > > > > > Ashok. >> > > > > > >> > > > > > **** To unsubscribe from si-list or si-list-digest: send e-mail to >> > > > > > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE >> > > > > > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. >> > > > > > si-list archives are accessible at http://www.qsl.net/wb6tpu >> > > > > > **** >> > > > > >> > > > > **** To unsubscribe from si-list or si-list-digest: send e-mail to >> > > > > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE >> > > > > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. >> > > > > si-list archives are accessible at http://www.qsl.net/wb6tpu >> > > > > **** >> > > > >> > > > >> > > > >> > > > >> > > >**** To unsubscribe from si-list or si-list-digest: send e-mail to >> > > >majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE >> > > >si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. >> > > >si-list archives are accessible at http://www.qsl.net/wb6tpu >> > > >**** >> > > >> > > >> > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ >> > > | NORTH EAST SYSTEMS ASSOCIATES, INC. | >> > > | ------------------------------------- | >> > > | "High Performance Engineering & Design" | >> > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ >> > > | Dr. Ed Sayre e-mail: esayre@nesa.com | >> > > | NESA, Inc. http://www.nesa.com/ | >> > > | Primrose Park Tel +1.978.392-8787 | >> > > | 5 LAN Drive, Ste 200 Fax +1.978.392-8686 | >> > > | Westford, MA 01886 | >> > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+ >> > > >> > > **** To unsubscribe from si-list or si-list-digest: send e-mail to >> > > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE >> > > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. >> > > si-list archives are accessible at http://www.qsl.net/wb6tpu >> > > **** >> > > -- > Scott McMorrow > Principal Engineer > SiQual, Signal Quality Engineering > 18735 SW Boones Ferry Road > Tualatin, OR 97062-3090 > (503) 885-1231 > http://www.siqual.com

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