RE: [SI-LIST] : Board Stackup Question

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From: Vikas.Mishra@smartm.com
Date: Wed Jun 06 2001 - 02:25:37 PDT


Hi Brian and All,

A couple of clarifications in this regard.

   As far as pwr/gnd plane capacitive coupling is considered, its effective only
   with small dielectric thickness. So I would like to suggest to use 2mil
   prepreg.
   We can also acheive the pwr/gnd decoupling by using following stackup
       S - G - P - S - S - G - S - S - G - S - S - P - G - S
      What can be the consequences on using this kind of stackup.
3. From EMI point of view, what are the consequences of routing high freqency
signals in top and bottom layer. Specially the clock signals(>133MHz freq.)

Thanks
Vikas

Date: Wed, 21 Mar 2001 09:43:26 -0800
From: "Moran, Brian P" <brian.p.moran@intel.com>
Subject: RE: [SI-LIST] : Board Stackup Question

C K,

Stay away from non symetrical stackups, as I think I saw someone suggest.

Neither of the stackups you offered provides any pwr/gnd plane capacitive
coupling, which is something you might want to consider. Some might argue
that having the ground planes on layers 2 and 11 might provide a bit better
EMC, but still lacking due to no high freq de-coupling

A better solution might be to add the extra two layers and pair up a couple
pwr/gnd planes, if you can afford it. A good 14 layer would be;

     S - G - S - S - P - G - S - S - P - G - S - S - G - S

This gives you three good stripline pairs, two coupled pwr/gnd pairs, an
outers for pin escape and non-criticals. Everyone has their own opinion on
this, but this is one of my favorite stackups. You can also use 2 mil
prepreg for the pwr/gnd pairs if thickness is an issue. If you want to use
Bc material you have to modify the stack to get pwr/gnd on opposite sides of
a core. In this case pair up the outer most ground planes instead of the
inner most.

Brian P. Moran
Signal Integrity Engineering
Desktop Products Group, Intel Corp.
Mail-Stop: FM6-45
1900 Priare City Rd, Folsom CA 95630
Phone:(916) 356-1912
Fax: (916) 377-1046

- -----Original Message-----
From: subramanya C K [mailto:subramanya.murthy@wipro.com]
Sent: Wednesday, March 21, 2001 2:20 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Board Stackup Question

Hello all ,
I have the following query regarding the Board stackup:

If U were supposed to design a 12 layer board with superior EMC, which
stackup among the following would U prefer and why ?

STACKUP-1: S1 G S2 S3 P S4 S5 G S6 S7 P S8
STACKUP-2: S1 P S2 S3 G S4 S5 G S6 S7 P S8
*S = Circuit (routing) Layer ; P = Power Plane ; G = Ground Plane

Next, is there any hazzard due to the power noise in 3rd and 4th circuit
layers (S3 and S4) of the first topology ? if yes, what's the reason
behind that and how do U overcome it ?
(same for S7 and S8 of second stackup)

Finally, if I am given the liberty of increasing the number of power
planes on the cost of circuit layers (say 4:4), will it create any
crosstalk among the tarces on the four circuit layers ? (because now
there are more number of high speed tracks bunched nearer than before)
If yes, is there any go for that ?

Thanks and Regards,

Subramanya C K
Tel: +91-80-8520408 Ext: 4179

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