RE: [SI-LIST] : basic design question

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From: Zabinski, Patrick J. (zabinski.patrick@mayo.edu)
Date: Tue Jun 05 2001 - 16:59:02 PDT


Adam,

There are a few options you might consider:

* Place a pair of buffers at the board interface, tie
both inputs to the tester signal, and
have each buffer drive an element of the "T". This
will result in point-to-point nets, which are much
easier to deal with.

* Ditto, but use a single clock-distribution chip.
Not much difference, other than reducing the capacitive
load the tester sees.

* Run the trace from the tester into the board as
far as you can, then split to the "T". At the top
of the "T", keep the two sides equal length and
less than 1/4 of the edge rate in length. The signal
will split in amplitude, and they will reflect, but
their reflections will constructively add, and the
resulting signal at the input of the receivers will
look like an edge of slower edge rate.

* If you cannot get the two sides of the "T" to be
less than 1/4 of an edge rate, then try slowing down
the egde with an R-C circuit at the tester input to
force the edge rate slower.

This is by no means an exhaustive list, but it should
give you a few ideas to try.

Pat

> I have a 133MHz DUT Board with 50 OHM traces, I have one
> output from the
> tester driving a signal which needs to reach the connector in
> two different
> locations but if I "T" the signal i will receive reflections
> on the signal
> is there another solution which would reduce reflections, and
> keep the
> signal clean.
>

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