RE: [SI-LIST] : Full swing CMOS nets without source resistors

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From: ruston, matt (ruston_matt@emc.com)
Date: Tue Jun 05 2001 - 08:29:06 PDT


Michael:

 I guess tolerance all depends on the spacings available in the BGA field,
sheet resistance used, resistor geometry (serpentine, bar, partial square),
other resistors desired on the board, etc. I seem to remember a small 22-25
ohm resistor might give around +/-25% or so (I may be wrong). Not too bad
for a series term.

 I forgot to mention that there is some CAD tool setup as well during board
design.

Matt

-----Original Message-----
From: Chan, Michael [mailto:Michael.Chan@compaq.com]
Sent: Tuesday, June 05, 2001 11:16 AM
To: ruston, matt; 'Degerstrom, Michael J.'; si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Full swing CMOS nets without source resistors

Matt:
     What is the typical tolerance of the resistor value integrate into the
PCB?

Regards,
Michael

-----Original Message-----
From: ruston, matt [mailto:ruston_matt@emc.com]
Sent: Tuesday, June 05, 2001 9:50 AM
To: 'Degerstrom, Michael J.'; si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Full swing CMOS nets without source resistors

Michael:

 Hi. Have you considered Ohmega layer technology? It can integrate the
resistors into the PCB for you. Things to consider are resistor tolerance,
added board costs, reliability (they claim no failures in the field in over
20 years), etc.

 It may do what you need it to do.

Later,

Matt

-----Original Message-----
From: Degerstrom, Michael J. [mailto:degerstrom.michael@mayo.edu]
Sent: Tuesday, June 05, 2001 10:29 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Full swing CMOS nets without source resistors

We are designing a board with many very high I/O
BGA parts. In some cases, the I/O strength/style
are selectable but there are many cases where
output impedances are not selectable and have
very low impedances of say 10-15 ohms. In the
past, with lower pin counts and less dense I/O,
very good signal integrity was obtained by adding
30-40 ohm series (source) termination resistors close to
the driving pins. But using resistors is not very
practical with this design due to the high I/O
count with multiple BGA packages separated by
only about .200".

Without resistors, the ringing (overshoot and then
ringback)is substantial. In some cases I wouldn't
be so concerned but many of the inputs are "LVTTL"
in which case the vendor MAY bias the threshold
closer to ground. Of course, in many cases, these
inputs are driven by "LVTTL" outputs which pull down
much harder than they pull-up and so the LOW state
ringing is higher than the HIGH state ringing.

Having said all this I'm hoping that some of you
can respond to me with some guidelines, techniques,
etc., that you use to obtain successful "resistorless"
designs. Here are some things that I have been
thinking about:

1) Don't worry about ringing unless the signals
haven't stablized before the input device is
clocked.

2) Rely on the clamps in the inputs to reduce
ringing and protect them from overvoltage.

3) Trust everything to the IBIS models - model
output to input(s) - if there are no glitches
then everything will work.

4) Lower the board impedance to 35-40 ohms to
reduce ringing - but what about increased power and
switching noise?

5) Terminate the top 20% "worst offenders".

6) Pick overshoot and ringback maximum values
and try to somehow design the nets to meet these
values. If don't think the parts can be placed
any closer however. What max. values of overshoot and
ringback do I chose?

Thanks in advance,

Mike

_______________________________________________________________
Mike Degerstrom Email: degerstrom.michael@mayo.edu
Mayo Clinic; 200 1st Street SW ; Rochester, MN 55905
Phone: (507) 538-5462 FAX: (507) 284-9171
WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html
_______________________________________________________________

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