Re: [SI-LIST] : Query on gtl+

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From: Bill.Cohen@taec.toshiba.com
Date: Tue Jun 05 2001 - 05:50:54 PDT


Hello Rajesh,

Our group in San Jose designed a GTL+
buffer about three years ago. It was difficult
to meet the slew rate spec. I think they finally
used some feedback control to meet the slew
rate over process/temperature/voltage.

Unfortunately, I don't have the details of the
actual spec. in regards to min./max. loading of the
bus. But I know there are test benches that our
group received from Intel to test the GTL+ IO
cell. These test benches were spice subcircuits.

Best Regards,

Bill Cohen
Toshiba America

rajesh.kaushik@st.com@silab.eng.sun.com on 06/05/2001 07:17:26 AM

Please respond to rajesh.kaushik@st.com

Sent by: owner-si-list@silab.eng.sun.com

To: si-list@silab.eng.sun.com
cc:
Subject: [SI-LIST] : Query on gtl+

Hello SI List,

I have a query regarding one of the GTL+ standard's specifications.
The standard specifies that "the driver slew rate should be between
0.3V/ns and 0.8V/ns". Output slew of a driver also depends on the load it
is driving. So does the above specification gives a range of load which
it can support? And if there is any such range then what is that?

Thanks in anticipation
Rajesh Kaushik

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