Re: [SI-LIST] : AGND & DGND stitching

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From: Ritchey Lee (leeritchey@earthlink.net)
Date: Fri Jun 01 2001 - 09:52:05 PDT


Henry Ott just penned a good article on this topic. It is in the June issue of
PC Design magazine. I recommend you get a copy and follow that advice.

Title: "Partitioning and Layout of a Mixed Signal PCB."

Lee

Ken Cantrell wrote:

> Bhavesh,
> Not sure if this will solve your problem, but I always use a stitch
> separation distance of lambda/20 of the fastest edge rate. This is from
> either one of Montrose's books, and of course, Ott's seminal work before
> that. The "bigger" picture is whether or not this is required. Opposing
> views state that if you design your lines/boards correctly, you won't have
> the residual coupling flux to begin with.
> I don't use single point grounds either. I guess the idea was to prevent
> low-frequency AC V&I from leaking into the DC frame and producing skew in
> the oscillator and noise on the DC power frame. The further away you are
> the more inductance, the more inductance the more the noise current time
> rate of change is slowed down thereby reducing Vcm. I don't subscribe to
> that theory. I think that might have been feasible at very low frequencies,
> but doesn't apply to today's technology. Multi-point provides the lowest
> inductance path to ground, and has worked best for me so far. On board
> physical separation, and even split ground planes are sometimes helpful
> especially in high current applications.
> Ken
>
> -----Original Message-----
> From: owner-si-list@silab.eng.sun.com
> [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Patel, Bhavesh
> Sent: Tuesday, May 15, 2001 7:41 PM
> To: SI_LIST (E-mail)
> Subject: [SI-LIST] : AGND & DGND stitching
>
> Hi! I needed some feedback regarding the concept of stitching AGND and DGND
> planes.
> >From some reference material that I have read:
> 1) AGND & DGND should be stitched at one point, this way you ensure the
> return point and do not create ground loops.
> Now, on a board that I have the designer stitched agnd and dgnd with
> shorting bars all over the place with no constraint i.e. number and location
> on top layer and bottom layer. Later, when the board was being debugged some
> of the chips that had both agnd and dgnd pins were seeing a huge potential
> difference which made some sections of the IC not to function properly.
> My take on this is that the multiple stitching points are giving rise to
> weird ground loops which create this potential difference.
> What is the best approach for connecting AGND and DGND and should the
> highest operating frequency on the board should play a role in the number of
> stitches .
> Thanks in advance
> Bhavesh Patel
>
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