From: dkhatri ([email protected])
Date: Fri Jun 01 2001 - 08:11:57 PDT
I am trying to come up with the best diff. clock topology for the
unbuffered DDR modules. Trying with different topology I get the better
signal integrity with the topology I like to have but the min/max flight
time is slower by ~200 ps than the rest of the other topology. I am trying
to get a feeling how much will this hurt us in the set up and hold time. Any
Appreciate your inputs.
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:12:12 PDT