[SI-LIST] : parasitic capacitance of PCB microvia

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From: Samuel Tilakraj (presam@hotmail.com)
Date: Mon May 28 2001 - 18:28:05 PDT


Hi SI-gurus,

I understand that PCB features such as the PTH and microvias can be a
limitation on PCBs designed for high freq application. I am interested in
studying this aspect, both in computational and physical terms.

In this regard, I would greatly appreciate any info on how I can compute EM
aspects, such as parasitic capacitance and inductance of PTH and microvias.
In particular, I would like to know how these can be modeled for vias of
different 3D geometries (such as cylinder & cone in solid or hollow (with a
given wall thickness)).

Thanks again and appreciate your time.

Samuel Tilakraj

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