**From:** ARiazi (*ARIAZI@prodigy.net*)

**Date:** Mon May 28 2001 - 18:11:35 PDT

**Next message:**Samuel Tilakraj: "[SI-LIST] : parasitic capacitance of PCB microvia"**Previous message:**Charles Grasso: "RE: [SI-LIST] : Frequency based on rise time for drivers"**In reply to:**Chandan: "RE: [SI-LIST] : EFFECT OF LUMPED LOAD ON TRANSMISSION LINES"**Next in thread:**Ken Cantrell: "RE: [SI-LIST] : EFFECT OF LUMPED LOAD ON TRANSMISSION LINES"

Chandan Wrote:

*> By the way, how does one decide the rise time length?
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*> Sometime in April, Abe Riazi (ServerWorks)
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*> provided us with the BELOW formula for critical
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*> length. (Refer to "Source termination of transmission
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*> line, April 23)
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*>
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*> Lc = k(Tr)/(Tpd)
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*> Where, Tr is rise time and Tpd is signal propagation
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*> delay.
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*> A good value for coefficient k is 1/6; and assuming
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*> FR-4 substrate
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*>
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*> Could someone derive this for me? or this this an
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*> empirical result?
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*>
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The origin of Critical Length can be found in

High-Speed Digital Design-A Handbook of Black Magic

Page 7, Equation 1.3:

Length of rising edge = rise time/delay

The critical length then emerges via simple relation:

Lc = k * (length of rising edge)

The coefficient k can assume a range of values including

1/2, 2/5, 1/3, 1/4, 1/6, 1/8, 1/10. The selection

k=1/6 is an excellent choice for many (but not all) applications.

*> I thought of using the following relationship:
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*> velocity = distance/time
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*> Therefore, Critical length = velocity of signals on
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*> the PCB * rise time
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*> Assuming a PCB propagation velocity that is half the
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*> speed of light,
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*> Critical length = 15cm/ns * rise time
*

Your assumption that PCB propagation velocity is half speed of

light ( or equivalently PCB signal propagation delay is twice propagation

delay of electromagnetic waves in free space) is correct.

Valuable insight can be gained by considering free space speed of light

( c ) and its reciprocal ( 1/c ) in several different units, i.e. :

c = 3E8 m/sec = 3E10 cm/sec = 30 cm/ns = 1.118E10 in/sec = 0.0118 in/ps

=11.8 in/ns

1/c = 84.67 ps/in = 0.08467 ns/in = 1.02 ns/ft

The equality 1/c = 1.02 ns/ft is approximately one half of a commonly used

value (e.g. 2 ns/ft ) for signal propagation delay on a PCB having FR-4

substrate.

The critical length expression you have given:

Critical length = 15cm/ns * rise time

appears based on k=1, which is regarded too large and rarely used.

My post dated March 27, 19999 contains additional information regarding

Critical Length .

Furthermore, comments by D.C. Sessions and Larry McMillan who detected

numerical errors in that post are quite instructive.

Best Regards,

Abe Riazi

ServerWorks

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**Next message:**Samuel Tilakraj: "[SI-LIST] : parasitic capacitance of PCB microvia"**Previous message:**Charles Grasso: "RE: [SI-LIST] : Frequency based on rise time for drivers"**In reply to:**Chandan: "RE: [SI-LIST] : EFFECT OF LUMPED LOAD ON TRANSMISSION LINES"**Next in thread:**Ken Cantrell: "RE: [SI-LIST] : EFFECT OF LUMPED LOAD ON TRANSMISSION LINES"

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