Re: [SI-LIST] : Board stackup

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From: Abdulrahman Rafiq (arafiq@cisco.com)
Date: Thu May 24 2001 - 14:06:52 PDT


You might try Applied Simualtions (Apsims) RLGC program )

Hassan Ali wrote:

> Hi All, (and NOT just SI Gurus ;-))
>
> Could anyone point me to a primer or provide me with guidelines on how best
> to decide on board stackup issues such as:
>
> - number of layers, layer heights, layout of layers (signal, ground, power,
> etc.)
> - board material (FR4, GETEK, etc.),
> - dimensions of single-ended and differential-pair transmission lines (trace
> width, trace thickness, trace spacing, etc.),
> - via types (through-hole, blind, buried, microvia, etc.) and via sizes
> (including pad/anti-pad sizes, hole size, trace-pad clearance, etc.)
>
> Thanks in advance.
>
> Hassan.
>
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--
===============================================================================
Abdulrahman A. Rafiq (AKA Abbey)
Hardware Engineer

CISCO SYSTEMS INC. Internet Systems Business Unit Catalyst 6000 Product Line/HSS Engineering Services Signal Integrity and Packaging Design Group (ASIC'S/Signal Integrity Group) 230 West Tasman Drive Mail Stop: SJ/G/2/3 San Jose, Ca 95134 (Bldg: G-2, Office: 227)

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