From: [email protected]
Date: Thu May 24 2001 - 06:46:52 PDT
XY,
Please see http://www.lexmark.com/sscg/ for a paper "1997 EMC Symposium
Design Considerations of Phase-Locked Loop Systems for Spread Spectrum
Clock Generation Compatibility". This paper discusses several aspects of
compatibility between different logic systems and SSCG.
For serial communications, the important parameters are the allowable frequency
deviation, cycle to cycle jitter and skew for any clock recovery or tracking
PLL.
SSCG can be used if the modulation characteristics do not violate the
communication
specifications. In our products we routinely use SSCG clocks (about 2.5%
deviation) to run our
processors, and use a separate non-spread or very narrow SSCG deviation
clock for such things as USB.
Most commercial SSCG clocks have various frequency modulation
deviation available from +/-0.25% to +/- 5% and are also capable of being spread
up or
down which deviates either above or below a set frequency. The modulation
profiles and frequency (30kHz to 50kHz) also vary from one vendor to another.
We only use the profile know as the "Lexmark Profile" which is perfectly
periodic
and is very controlled. Some SSCG like implementations may not be as
controlled making it difficult to compare against communication specifications.
Also, 133 MHz SSCG clock chips have been on the market for quite some time for
PC's, which are widely used and there is really no limit on high a SSCG
frequency
can be created.
You mentioned the case where both receiver and transmitter are using SSCG
clocks.
In this case, it may be possible to synchronize the two modulation profiles so
that the
instantaneous frequencies are the same which reduces the frequency difference at
both ends of the line. I do not know if this feature is currently available but
it is possible.
The net of it is that SSCG can be modified to be used in many designs at most
any
frequency as long as the communication method allows frequency to vary.
The communication standard mentioned previously by John Barnes requires a clock
that
is not modulated so SSCG should not be used in those. If you would like to
discuss it more
please write directly to me.
Dr. Keith Hardin
Lexmark International Inc.
[email protected]
Please respond to x Ye <x_ye_2001%[email protected]>
To: si-list%[email protected]
cc: (bcc: Keith Hardin/Lex/Lexmark)
Subject: [SI-LIST] : Spread Spectrum in High Speed Serial Design
Hi all,
I have a question about using SSC (Spread Spectrum Clock) in High Speed serial
design. There has been concerns that if the transceiver and the receiver use
different clocks (and both are SSC), the receiver may have difficulty to track
the bit drift due to the timing difference (which is somewhat 1 bit drift
every 200 bits for a 0.5% down-spread). Anybody has the experience or any
comment?
Thanks,
XY
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