RE: [SI-LIST] : PCI BUS: UNEQUAL LOADING

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From: Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Date: Tue May 22 2001 - 06:39:49 PDT


> Assuming that devices on a PCI bus are connected in a
> daisy chain, all the drivers - except those at the
> ends of the PCI bus - "see" a line of characteristic
> impedance that is half the value of the loaded
> characteristic impedance.
>
> 1. What are the adverse effects of this unequal
> loading of the PCI bus drivers?
> 2. Is there any other way to avoid this situation?
 
I suppose you could add parallel terminations on both ends of the bus, maybe
using RC terminations to reduce the DC power consumption. But I don't think
I'd recommend it. PCI devices weren't really designed with such loading in
mind, and I don't know if you might run into trouble with some devices if
you did.

> In order to ensure that the PCI devices at the end of
> the bus also "see" the same value of characteristic
> impedance, I would like to extend the PCI bus on both
> ends (i.e., I would like to add an extra inch prior to
> the first device and another inch of trace after the
> last device).
 
Probably not worth the effort. The driver near the end would see the two
traces for only about 300 ps.

I think the extra stub might increase ringing. You might think of the stub
as a tuned circuit with very high Q since it has no active device on it, not
even clamps. But try some simulations and see what you get.

Keep in mind that PCI is not a controlled impedance bus. Efforts were made
to control many things, all of which help, but PCI is a low-cost commodity
bus and it has some pretty wide tolerances. The range of driver source
impedances exceeds the 2:1 effective load impedance you are asking about.

Regards,
Andy

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