From: Wang Xiao-yun ([email protected])
Date: Mon May 21 2001 - 18:20:32 PDT
There is a mail from Bob's mailbox in Electronic Design criticizing the
spread-spectrum clock scheme from analog point of view.
http://www.planetee.com/planetee/servlet/DisplayDocument?ArticleID=12819
However, Bob Pease did not explicitly show his opinion and it's not likely
he's in this "all-digital" forum.
As a digital designer of communication system, the scheme is probably
the last straw I will grab to pass the EMI verification, because the jitter it
induces may even give me much more headache to make the design
functioning.
Although I totally agree the Hershey's is delicious 8-)
At 11:17 01-5-21 -0700, Larry Miller wrote:
>That is a very real problem. I have not seen jittered clocks used at really
>high speeds (>50 MHz).
>
>However, it would seem that you could calculate the parameters rather
>directly.
>
>I've never seen any that had as much wibble as you say; a few percent of a
>unit interval would be in order unless the modulation frequency is low
>enough that your receiver PLL could track it.
>
>Larry
>
>-----Original Message-----
>From: x Ye [mailto:[email protected]]
>Sent: Monday, May 21, 2001 10:11 AM
>To: [email protected]
>Subject: [SI-LIST] : Spread Spectrum in High Speed Serial Design
>
>
>Hi all,
>
>I have a question about using SSC (Spread Spectrum Clock) in High Speed
>serial
>design. There has been concerns that if the transceiver and the receiver use
>different clocks (and both are SSC), the receiver may have difficulty to
>track
>the bit drift due to the timing difference (which is somewhat 1 bit drift
>every 200 bits for a 0.5% down-spread). Anybody has the experience or any
>comment?
>
>Thanks,
>
>XY
>
>
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Wang Xiao-yun
Shanghai, China
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