**From:** Scott McMorrow (*[email protected]*)

**Date:** Mon May 21 2001 - 14:07:25 PDT

**Next message:**Larry Miller: "RE: [SI-LIST] : Package power rating"**Previous message:**Zabinski, Patrick J.: "RE: [SI-LIST] : Package power rating"**In reply to:**Todd Westerhoff: "RE: [SI-LIST] : Accuracy"**Next in thread:**Dr. Edward P. Sayre: "[SI-LIST] : Accuracy vs. engineering judgement"

Todd,

I cannot speak for the accuracy of skew prediction at the chip level.

However, especially with source synchronous busses, timing (skew)

is still based upon the most accurate error analysis that we can do.

In your example, lets assume +/- 50 ps skew at the driver inputs

and +/- 50 ps skew at the receiver outputs. Total worst case skew

without other effects is +/- 100 ps.

Skew due to package, and SSO effects is probably +/- 100 ps

Skew due to board crosstalk, routing and ISI effects is probably +/- 100 ps.

Total skew = +/- 300ps.

If +/- 25 ps of board effects are unaccounted for then this

would constitute an error of 8%. Not a significant error percentage,

but certainly a noticable one. My guess is that in many cases there

is much more than +/- 25 ps of effects that are missing from many

end to end system simulations.

If we know that there are board effects not account for by simulation,

we can certainly guardband for them. For our hypothetical system the

total system skew would then be +/- 325 ps.

However, one must be quite careful with these "simulation modeling errors" and

be sure that there are not cumulative errors that can creep up. Such

cumulative errors can occur due to cascaded models, each with errors

that occur either in their fundamental modeling aspects, or due to simulator

algorithm errors. (The old HSPICE w-element cascaded section problem

is an example of this. Hopefully fixed by now.) Fortunately, in source

synchronous systems, cascaded modeling errors tend to drop out of the

equation, since for skew we are dealing with relative skew, not absolute

timing numbers. In that case, if all signals which require low skew are

"nearly identical", and also nearly identical in characteristics with the strobe,

( this is Scott's same animal rule), then most of the small modeling errors

drop out because of symmetry.

regards,

scott

-- Scott McMorrow Principal Engineer SiQual, Signal Quality Engineering 18735 SW Boones Ferry Road Tualatin, OR 97062-3090 (503) 885-1231 http://www.siqual.comTodd Westerhoff wrote:

> Scott, > > Very good points - but they beg the question: > > If I'm doing my own ASIC, and even if I characterize the behavior through > the I/O buffers to the Nth degree with HSpice (or whatever) - > > - how good, on average, is the internal skew information I can get for the > path delays inside the ASIC?. This is the same question as before: if I can > only predict the signal arrival times at the inputs of the output buffers to > +/- 50 pS - how important are 25 pS effects at the board level? And more > importantly, what level of timing resolution for internal ASIC delays should > be considered "good" for a modern device? > > Todd. > > Todd Westerhoff > SI Engineer > Hammerhead Networks > 5 Federal Street > Billerica, MA 01821 > [email protected] > ph: 978-671-5084 >

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**Next message:**Larry Miller: "RE: [SI-LIST] : Package power rating"**Previous message:**Zabinski, Patrick J.: "RE: [SI-LIST] : Package power rating"**In reply to:**Todd Westerhoff: "RE: [SI-LIST] : Accuracy"**Next in thread:**Dr. Edward P. Sayre: "[SI-LIST] : Accuracy vs. engineering judgement"

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