RE: [SI-LIST] : Spread Spectrum in High Speed Serial Design

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From: Larry Miller (ldmiller@rhapsodynetworks.com)
Date: Mon May 21 2001 - 11:17:04 PDT


That is a very real problem. I have not seen jittered clocks used at really
high speeds (>50 MHz).

However, it would seem that you could calculate the parameters rather
directly.

I've never seen any that had as much wibble as you say; a few percent of a
unit interval would be in order unless the modulation frequency is low
enough that your receiver PLL could track it.

Larry

-----Original Message-----
From: x Ye [mailto:x_ye_2001@usa.net]
Sent: Monday, May 21, 2001 10:11 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Spread Spectrum in High Speed Serial Design

Hi all,

I have a question about using SSC (Spread Spectrum Clock) in High Speed
serial
design. There has been concerns that if the transceiver and the receiver use
different clocks (and both are SSC), the receiver may have difficulty to
track
the bit drift due to the timing difference (which is somewhat 1 bit drift
every 200 bits for a 0.5% down-spread). Anybody has the experience or any
comment?

Thanks,

XY

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