From: Todd Westerhoff ([email protected])
Date: Mon May 21 2001 - 07:37:15 PDT
Here's a question for the group that I'm hoping will invoke some discussion:
I've seen and heard lots of comments over the years about the need for
"accurate" SI analysis. We've had any number of threads over the past few
months discussing effects that would produce variances of 50 pS or less in
simulation results, and the need for such levels of accuracy.
But what about timing? After all, signal integrity is only one component of
system analysis; you need to put SI analyses together with component timing
data to figure out whether your system works or not. And what's the point
of having 15 pS of accuracy in your SI analysis results if you only know
component timing to within 250 pS?
I'm interested in how people are coupling SI analysis with timing data, for
both common-clock and clock-forwarded architectures, to close system-level
timing. I'm really interested in what level of accuracy people have for
timing data, and at what level. At the commercial component level, it seems
to me there's so much margin in the timing numbers that many of the finer
effects we discuss here are swamped out. And even when you have internal
timing data for an ASIC you're designing, well, it seems to me that if you
know your timing and skews to within 25 pS, you're doing better than most.
5 Federal Street
Billerica, MA 01821
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:12:02 PDT