Re:[SI-LIST] : Signals crossing plane splits, return currents etc revisited..... ..

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From: Jason Miller - WGS-VLSI Engineering (Jason.R.Miller@Sun.COM)
Date: Wed May 16 2001 - 11:47:18 PDT


Hi Michael,

The current return path for signal 2 will be different for different switching
patterns (i.e. high to low and low to high). For a low to high transition the current
will return via the power plane primarily. Therefore, the current return path (and
loop inductance) will be disrupted by the presence of the VDD split plane in the low
to high transition. The loop inductance should increase because the split will force
the current to deviate from the path of least inductance. However, the presence of the
tightly coupled upper ground plane should reduce the impact of this to some degree. I
believe the impedance of the trace would be fairly insensitive to the plane split
because signal 2 is significantly offset from the VDD plane.

Jason Miller

        From: "Greim, Michael" <mgreim@sonusnet.com>
        To: "SI_LIST (E-mail)" <si-list@silab.eng.sun.com>
        Subject: [SI-LIST] : Signals crossing plane splits, return currents etc
revisited..... ..
        MIME-Version: 1.0
        
        Hi All,
         
        There's been alot of talk about the evils of routing over plane splits,
        regarding impedance bumps, impact to return currents etc. I ran
        into an interesting structure the other day that I thought might be
        some good food for discussion:
         
                    --------------------------------- GND
                                2 mil BC
                    --------------------------------- Voltage with plane splits
                                Sig 1
                                Sig 2
                    --------------------------------- GND
         
        In the above structure, Sig 1 was routed with route keep outs across
        the split (and it was obeyed). However, Sig 2 did not have route keep
        outs and some of the voltage splits are crossed. Spacing between each
        sig to plane is 4 mils and to each other is four mils. Given the proximity
        of the upper ground to the split plane the case has been made that the
        impedance impact to sig 2 is minimal and as the adjacent plane to it is
        solid that the current return path is minimally to not impacted. So whaddya
        think? and can it be said that if one must deal with plane splits that a
        structure like this is viable? Given the density of many of today's
        boards,
        is adding layers to avoid routing over splits on sig 2. needlessly
        increasing
        the cost of the fab?
        Note: For the purposes of this discussion the moat surrounding these power
        islands can be considered 25 mils.
        
        Best Regards,
        
        Michael C. Greim Sonus Networks
        mgreim@sonusnet.com 978-589-8336
        
        Making the world safe for digital signals everywhere
        
        And all this science I don't understand
        It's just my job six days a week
        
        The time is gone. The email's over
        Thought I'd something more to say......
        

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