From: Shahar Eytan ([email protected])
Date: Wed May 16 2001 - 10:30:31 PDT
In my application I have a Serdes (2.5Gb/s PECL) connected to a differential
4X (4 differential pairs in each direction)connector. All the differential
TX lines and the differential RX lines are grouped together in this
I want to have a DC blocking capacitor (0.01uF in 0402 package) on the RX
lines close to the connector have a via and route them all the way to the
Serdes in the print side.
From designs I've seen the capacitor should be as close as possible to the
This cause a very dense capacitors and vias placement very close to the
I'm very afraid of the Xtalk between the pairs. The space between the pairs
in the output of the connector is around 1.2mm.
The trade off I'm facing is whether to make the trace between the connector
and the capacitor in every second pair longer, thus having another
discontinuity on the pair, or maintain the minimal length but risking the
design in means of Xtalk.
I hope I had managed to explain my problem, looking forward for your help.
Mellanox Technologies Ltd.
mailto: <[email protected]>
Tel: 972-4-9593244 ext 264
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:59 PDT