Re: [SI-LIST] : LVDS I/Os from vendors

About this list Date view Thread view Subject view Author view

From: D. C. Sessions (si-list@lumbercartel.com)
Date: Sat May 12 2001 - 06:57:08 PDT


On Thursday 10 May 2001 11:01, Sivaraman Chokkalingam wrote:
 
> I'd like to get in touch with anyone who has had experience evaluating LVDS
> I/Os from vendors ? I'm talking about Intellectual Property (for example -
> gds2 layout) that can be integrated with the rest of the logic on a chip -
> not independent packaged components.
>
> I'm interested in knowing about general problems that were encountered in
> the process of integrating these things and general problems found on
> silicon because of these.

Speaking as an I/O designer, here are some of the issues that we struggle with:

1) Power. LVDS is hot stuff, but a good design wastes less power than a poor one.
2) Receiver Jitter.
2a) Check for delay consistency across common-mode range on the receivers.
    LVDS' wide input common mode range usually requires the use of two input
    differential pairs (ine NMOS, one PMOS) and a crossover network. Getting
    the combination to work consistently across common-mode is Not Trivial.
2b) Check for delay consistency across input amplitude. Due to intersymbol
    interference (etc.) the receiver won't always be seeing the same amplitude, so
    there will be some delay variation. Less variation is, of course, good.
2c) Bandwidth. Receivers often respond fairly quickly to a transition but continue
    to change state internally for quite a while afterward. This shows up in delay
    reduction as pulse width is reduced.
2d) Net delay. The longer the total delay through the receiver, the more absolute
    variation will show up from (e.g.) voltage variation. Which is a good thing to
    check for anyway. If you're sensitive to skew between signals, this is even more
    important.
3) Driver Jitter.
3a) Bandwidth. Same comments as (2c).
3b) Symmetry. Chip cores are typically single-ended logic, while LVDS is differential.
    The single-ended to differential conversion will always introduce some rise/fall
    asymmetry, but a good design will have less of it. A great design will have the final
    stage latches and multiplexers in the I/O cell itself so that the conversion happens
    before the final synchronization.

That's my short list. It's a lot better if you can get your hands on the SPICE models
and run your own tests, but if you have good support you should be able to crank
up a deck to test these things and have the vendor run them.

-- 
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat.                |
+--------------- D. C. Sessions <dcs@lumbercartel.com> --------------+

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:56 PDT