RE: [SI-LIST] : MECL System Design Handbook

About this list Date view Thread view Subject view Author view

From: Issa, Elie (Elie.Issa@compaq.com)
Date: Fri May 11 2001 - 11:57:23 PDT


You could have a fixture which would allow you to measure a TDR rise time
10-90%
in the upper 20ps. But other questions could be still valid to decide if a
particular discontinuity would be visible or not such as,
am I probing close enough the discontinuity so that reflections
from the board topology and losses would not degrade my rise time further?
Since what counts is the rise time when it hits the discontinuity.
What are the effective dielecrtic and physical length? This is
important to know to compare the electrical length of the discontinuity
versus the wavelength of the signal.

-----Original Message-----
From: Dima Smolyansky [mailto:dima@tdasystems.com]
Sent: Thursday, May 10, 2001 5:19 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : MECL System Design Handbook

Fred:

We have been able to deliver 30-35ps to the board with a cable that we
supply to our customers. Nothing too special, either, just a low loss cable.
That is a reflected TDR 10-90% rise time. I have a screen capture of this
data, but do not want to risk sending it to the newsgroup. Anybody
interested please contact me in person.

===================
Dima Smolyansky
TDA Systems, Inc.
11140 SW Barbur Blvd., Suite 100
Portland, OR 97219
(503) 246-2272
(503) 246-2282 (fax)
(503) 804-7171 (mobile)
http://www.tdasystems.com
The Interconnect Modeling Company(TM)

----- Original Message -----
From: "Fred Balistreri" <fred@apsimtech.com>
To: "Dima Smolyansky" <dima@tdasystems.com>
Sent: Thursday, May 10, 2001 11:11 AM
Subject: RE: [SI-LIST] : MECL System Design Handbook

> I'm not from Missouri but I still have yet to see proof of this. I said a
> single bend.
> But yeh I'm not that closed minded so I'll play. What is the voltage and 0
> to 100% rise
> time that you CAN get to board?
>
> Best Regards,
> Fred Balistreri
>
> -----Original Message-----
> From: owner-si-list@silab.eng.sun.com
> [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Dima Smolyansky
> Sent: Thursday, May 10, 2001 11:32 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : MECL System Design Handbook
>
>
> Fred:
>
> With a little skill, one does not have to be "lucky" to get fast TDR rise
> time to the board. If one uses good quality cables low loss and probes,
and
> delivers the available rise time from TDR to the board, one can observe
the
> right angle bends in question.
>
> Thanks,
>
> ===================
> Dima Smolyansky
> TDA Systems, Inc.
> 11140 SW Barbur Blvd., Suite 100
> Portland, OR 97219
> (503) 246-2272
> (503) 246-2282 (fax)
> (503) 804-7171 (mobile)
> http://www.tdasystems.com
> The Interconnect Modeling Company(TM)
>
>

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:56 PDT