From: Degerstrom, Michael J. (email@example.com)
Date: Fri May 11 2001 - 07:14:38 PDT
I think the answer that Selva was looking for is that loads are typically
by their ESD protection which is often a capacitance of several picofarads
more. Years ago with TTL and CMOS, the edge rates were slow enough that
IC loads and even pcb wiring was adequately modeled with simply a load
capacitance and inductance and resistance were second order effects.
Presently many vendors also provide inductance and resistance numbers
for their ICs. The inductance can make modest difference depending on
the package used.
Mike Degerstrom Email: firstname.lastname@example.org
200 1st Street SW
Gugg. Bldg. RM 1042A Phone: (507) 284-3292
Rochester, MN 55905 FAX: (507) 284-9171
From: Inmyung Song [mailto:email@example.com]
Sent: Friday, May 11, 2001 3:16 AM
To: selvaraj subramanian ; firstname.lastname@example.org
Subject: Re: [SI-LIST] : Load - Capacitance
I guess one of the feature of capacitor is charging and discharging.
That mean, the capacitor charges the overshoot or undershoot but the edge
become longer than no capacitor. Is it right?
----- Original Message -----
From: selvaraj subramanian <mailto:email@example.com>
To: firstname.lastname@example.org <mailto:email@example.com>
Sent: Friday, May 11, 2001 3:10 PM
Subject: [SI-LIST] : Load - Capacitance
Why the loads are termed in terms of capacitance rather than resistance or
**** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:55 PDT