From: Mike LaBonte ([email protected])
Date: Thu May 10 2001 - 06:46:35 PDT
Since on-the-fly buffer delays are calculated by a test circuit
embedded in a regular net simulation circuit, the code for doing
this circuit generation is somewhat different from the library
buffer delay simulation code, which is able to create a simpler,
stand-alone circuit. If one works and the other doesn't, report
it to Cadence.
The only hint I can offer is that the simulation timestep is
chosen based on the total circuit contents, and may be different
in each case. If the DesignLink has extremely short transmission
lines lengths, for example, that may force the timestep down in
the net simulation. But the buffer delay simulations have no
Also, library buffer delay simulations run a fairly long duration,
to properly measure heavy test loads. Although simulations with
DesignLinks are often fairly long, the simulations still may not
be long enough. SPECCTRAQuest does not consider buffer delay test
loads when choosing simulation durations. You might try a longer
As long as library delays work you should be all set anyway.
> "Greim, Michael" wrote:
> Hi All,
> I am seeing something odd in specctraquest 13.6 and wanted to
> solicit your opinion to see if this is a feature of the tool or
> perhaps something else is going on. Simply put, any time
> that I try a waveform simulation that includes a design link
> and calculates buffer delays on the fly, the simulation fails
> at all three speeds. If I run the sim using delays from the library,
> the simulation passes and when I calculate buffer delays in
> the model editor that passes as well. In both cases I am in
> clined to believe the results.
> Any thoughts?
> Best Regards,
> Michael C. Greim Sonus Networks
> [email protected] 978-589-8336
> Making the world safe for digital signals everywhere
> And all this science I don't understand
> It's just my job six days a week
> The time is gone. The email's over
> Thought I'd something more to say......
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