From: Cosmin Iorga ([email protected])
Date: Wed May 09 2001 - 14:28:50 PDT
Hi Michael,
I would check the "Elect. Conductivity" value in the stack-up before extracting
the topology (In SpecctraQuest window -> Board -> Edit Stack-up). I've seen
cases when this value is too high, thus, the DC resistance of the trace is
in the kohm range. One more detail, if your trace is on an internal layer
you need to check also the conductivity of the other layers. I've seen a case
in 13.6, when a high value set for the top layer was used for the internal
layers too.
Let me know the result.
Cosmin
--------------------------------------------------------------------------------
> From: "Greim, Michael" <[email protected]>
> To: [email protected]
> Cc: "Greim, Michael" <[email protected]>
> Subject: [SI-LIST] : specctraquest waveform sims fail with design link and
buffer dela ys on the fly......
> Date: Wed, 9 May 2001 15:32:15 -0400
> MIME-Version: 1.0
>
> Hi All,
>
> I am seeing something odd in specctraquest 13.6 and wanted to
> solicit your opinion to see if this is a feature of the tool or
> perhaps something else is going on. Simply put, any time
> that I try a waveform simulation that includes a design link
> and calculates buffer delays on the fly, the simulation fails
> at all three speeds. If I run the sim using delays from the library,
> the simulation passes and when I calculate buffer delays in
> the model editor that passes as well. In both cases I am in
> clined to believe the results.
>
> Any thoughts?
>
>
> Best Regards,
>
> Michael C. Greim Sonus Networks
> [email protected] 978-589-8336
>
> Making the world safe for digital signals everywhere
>
> And all this science I don't understand
> It's just my job six days a week
>
> The time is gone. The email's over
> Thought I'd something more to say......
>
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