From: Wang Xiao-yun (email@example.com)
Date: Wed May 09 2001 - 04:06:23 PDT
As far as I know, the data should be sampled at the edge of the clock no
matter it's differential or single end. If you have a fixed but asymmetrical
duty cycle, you will still make your circuit work as long as the setup/hold
margin is positive. If you have a varying duty cycle, it will become jitter and
you will have more to worry about.
So far I don't have experience on double (or quad) data rate, but my feeling
is an asymmetrical duty cycle will do you harm in those cases.
At 21:53 2001-5-7 +0000, Saeen Malik wrote:
>I have a dumb question. This relates to the LVDS interface for Sonet framers.
>I was of the opinion that the LVDS interaface would always sample the data
>at the crossing
>of the differential clock (I mean crossing of the p and n of the diff clcok).
>If this is true, then it would make the interface independent of the duty
>cycle of the clock.
>(since as the duty cycle of p increases the duty cycle of n decreases
>keeping the distance between
>the two crossing points the same). But, it appears that that is not the
>way the receiver works.
>(atleast from the documentation). Can someone explain how does it really
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